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Wireless Sensor Network

Wireless Sensor Network. A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution* by Banit Agrawal. *Paper published in CASES 2005 by U Michigan Group. Outline. Introduction Applications of wireless sensor networks

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Wireless Sensor Network

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  1. Wireless Sensor Network A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution* by Banit Agrawal *Paper published in CASES 2005 by U Michigan Group Banit Agrawal @ UCSB

  2. Outline Introduction Applications of wireless sensor networks Wireless Sensor Network (WSN) Architecture WSN’s Microprocessor UMich first generation processor UMich second generation processor Conclusion Banit Agrawal @ UCSB

  3. What is wireless sensor network Wireless Sensor Network (WSN) Network of many small distributed computers for processing the sensor data Usually consists of microprocessor, memory, transceiver, sensing device, battery/energy scavenging unit, etc Resource constrained Everything optimized for low-energy operations Banit Agrawal @ UCSB

  4. Current Challenges Energy Conservation Limited Computation/Storage Scalability Fault-tolerance Routing/Communication Bandwidth Autonomous and Distributed Systems Security Banit Agrawal @ UCSB

  5. Applications (1) Environmental Monitoring Habitat Monitoring Integrated Biology Structural Monitoring Building/Border/Battlefield detection Road/traffic monitoring Health monitoring Banit Agrawal @ UCSB

  6. Applications (2) Business Applications Supply Chain Management Expired/Damaged Goods Tracking Automatic Checkout Systems Security, surveillance Context-aware computing Automation Banit Agrawal @ UCSB

  7. WSN Node Architecture Ref: Energy-Aware Wireless Microsensor Networks Banit Agrawal @ UCSB

  8. Berkeley Motes Banit Agrawal @ UCSB

  9. Flash RAM Processor 10/100 Ethernet Address/Data Bus Preprocessor Interface Modular Wireless and Digital Interfaces Imager Module Imager Interface RF Modem 1 RF Modem 2 Digital I/O GPS Analog Front End Multi- Channel Sensor Interface DSP Preprocessor Sensoria SGATE hardware Banit Agrawal @ UCSB

  10. UCLA Sensor Nodes Banit Agrawal @ UCSB

  11. MIT AMPS Banit Agrawal @ UCSB

  12. Intel StarGate Banit Agrawal @ UCSB

  13. Micro Controller Sensors Addr/Data Radio Addr/Data Event Processor Message Processor System Bus Interrupt Power Ctrl Data Filter SRAM Timer Harvard’s University (ISCA’05) Banit Agrawal @ UCSB

  14. Telos 4/04 Robust Low Power 250kbps Easy to use WeC 99 “Smart Rock” Rene 11/00 Dot 9/01 Mica 1/02 Small microcontroller 8 kB code 512 B data Simple, low-power radio 10 kbps ASK EEPROM (32 KB) Simple sensors Mica2 12/02 38.4kbps radioFSK Demonstrate scale • Designed for experimentation • sensor boards • power boards NEST open exp. Platform128 kB code, 4 kB data40kbps OOK/ASK radio512 kB Flash Spec 6/03 “Mote on a chip” Berkeley’s Experimental Platform Services Networking TinyOS Ref: HotChips 2004 – “Mote Evolution…” Banit Agrawal @ UCSB

  15. Mote Evolution Ref: HotChips 2004 – “Mote Evolution…” Banit Agrawal @ UCSB

  16. WSN’s Microcontroller AT/ATmega/ATMEL (AVR) Family TI Family Intel XScale StrongARM Harvard’s microcontroller UMich’s first generation processor UMich’s second generation processor Banit Agrawal @ UCSB

  17. Processor Requirements Banit Agrawal @ UCSB

  18. Voltage Reduction Not Performance, Energy is important. Banit Agrawal @ UCSB

  19. Sensor Network Applications Representative set to evaluate architecture Banit Agrawal @ UCSB

  20. Optimizing Energy Efficiency Reduce the area to minimize the static power Transistor utility must be maximized CPI must be minimized Banit Agrawal @ UCSB

  21. Processor’s Characteristics 12-bit RISC ISA 8-bit datapaths Flexible Operand Handling Application specific instructions Prefetch mechanism Memory Architecture Branch speculation and out-of-order execution Banit Agrawal @ UCSB

  22. ISA: RISC Encoding 12-bit RISC encoding simple decoding logic Reducing code-density and hence area to reduce the leakage energy 96.2% encoding efficiency Banit Agrawal @ UCSB

  23. ISA Organization Banit Agrawal @ UCSB

  24. ISA Design Load-store architecture 8 registers Simple to design and pipeline 2-operand based design Preserve bit to save the source Various addressing modes available Banit Agrawal @ UCSB

  25. ISA Design (2) Micro-operations Application specific instructions Efficient pointer and carry manipulation Event scheduler control Timer control Reduction in code-size Banit Agrawal @ UCSB

  26. Memory Optimizations Data memory predecode architecture [May not be useful for pointers] Banit Agrawal @ UCSB

  27. Memory Optimizations (2) Instruction memory predecode architecture 2 words and automatically increment the page when PC reaches the end of page Banit Agrawal @ UCSB

  28. Processor pipeline design 3-stage pipeline [optimum, not 4 not 2] Banit Agrawal @ UCSB

  29. Microarchitectural Optimizations Out-of-order execution Taken branch speculation Banit Agrawal @ UCSB

  30. Results Banit Agrawal @ UCSB

  31. Results: Contributions Storage unit and other components Banit Agrawal @ UCSB

  32. Related Works 8-bit ATmega - 1.5 nJ/instruction Clever Dust 2 – 12 pJ/instruction StrongARM/XScale - 1nJ/instruction SNAP/LE – 24 pJ/instruction Umich first generation – 1.6 pJ/instruction Umich second generation – 600fJ/instruction Banit Agrawal @ UCSB

  33. Conclusion Energy-efficient processor (600 fJ/instruction, will run 312 years on single AAA) Microarchitectural and ISA optimizations to reduce the leakage energy IBM 130nm fabrication Intra-ocular pressure sensor Banit Agrawal @ UCSB

  34. Thanks for your attention. Questions ? Banit Agrawal @ UCSB

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