On the Introduction of Reconfigurable Hardware into Computer Architecture Education

1. On the Introduction of Reconfigurable Hardware into Computer Architecture Education Ross Brennan rbrennan@iee.org

2. Introduction • We will talk about the current microprocessor design project, which has been undertaken by students at Trinity College for the past 20 years • Discuss the motivation behind creating an updated version of this design project • Discuss the prototyped microprocessor project board • Finally, we will discuss future work leading on from the development of this prototype

3. Background and Related Work • Using custom hardware and reconfigurable logic devices to aid in the teaching of computer architecture is not a new concept • Previous efforts have concentrated on: • Designing and implementing custom hardware and simulation tools • Designing and implementing custom HDL processor models for teaching purposes • Developing project boards based around dedicated soft-CPU architectures • Without major updates to the processor models, these implementations cannot grow in complexity

4. The Current Design Project • Designed around the Motorolla MC68008 CISC microprocessor • 8 MHz system clock • 8-bit data bus • Uses GALs to implement “glue-logic” • Two serial ports implemented using ACIAs and MAX232s • Connections are wire-wrapped together by students • Monitor program implemented in assembler by students

5. Teaching Objectives • To adopt a “hands-on” approach towards teaching computer architecture concepts to students • To show students the differences between various processor architectures (RISC vs CISC, etc) • To allow students to design and implement Instruction Set Architectures (ISAs) • To enable students to observe real time behaviour of systems using logic state analysers

6. Prototyping the New Design [1] • Requirements: • Backwardly compatible with the current design project • Highly reconfigurable • Students to implement required system “glue-logic” • Students should be able to develop a basic operating system • A standardized bus interface was developed based around the MC68008 protocol • Can use multiple synthesisable HDL processor models for use as long as they implement the standardized bus interface • One such model already available is the LEON P-1754 processor

7. Prototyping the New Design [2] • Diagram of the layout for a single PROM system • Control logic is implemented in a CPLD or FPGA using a HDL • Connections are made by wire-wrapping components together

8. About LEON P-1754 • Initially developed by the ESA • Aimed for use in satellite control systems • Synthesisable VHDL model of a 32-bit processor • Highly configurable • Can remove unwanted internal peripherals • Released open source under the GNU LGPL • Now maintained by Jiri Gaisler

9. Main Processor Features • RISC architecture • SPARC V8 compliant integer unit • 5-stage instruction pipeline • On-chip AMBA AHB/APB • 32-bit, 33 MHz Master/Target PCI Interface • Parallel I/O Port • 2 Internal UARTs • Internal Debug Support Unit Diagram of the LEON core from Gaisler Research

10. LEON [1] • Reduce complexity where possible • Use 8-bit data bus option (for wire-wrapping) • Ability to disable non-essential components using a graphical configuration tool • Removable PCI interface • Removable FPU • Removable SDRAM controller • Software tools available from Gaisler Research • LECCS compiler (free for student use) • TSIM processor simulator (free for student use)

11. LEON [2] • Reduced clock speed • Operates at 6.25 MHz • Advantageous for wire-wrapping • Removable internal caches • Simplifies processor operation • Only method of observation via the bus • Modified bus transaction protocol • Similar to MC68008 bus transaction protocol • Students required to add external bus signaling • Removable internal memory map • Students are required to implement external logic instead

12. The Final Prototype Picture of the final prototyped design on the VirtexII prototyping board.

13. Future Work • Finalize the prototyped design • Design and build a prototype board capable of supporting multiple user configuration PROMs • Take advantage of the different LEON processor configuration options for tailoring the complexity of the system • Design and build a daughter board for use with the main project board (PCI/FPU/Ethernet/32-bit bus/etc) • Evaluate different HDL processor models for use with the project board

14. Conclusions • The prototyped design successfully proved that the LEON model was suitable for use in place of the MC68008 • The groundwork for designing a fully operational hardware system was put in place • Reconfigurable underlying hardware • Scope for further development