Data Synchronization Issues in GALS SoCs

1. ICS- FORTH Data Synchronization Issues in GALS SoCs Rostislav (Reuven) Dobkin and Ran GinosarTechnion Christos P. SotiriouFORTH

2. Outline • The Problem • Synchronization Failures in GALS SoCs • Three solutions: • Timing verification • Synchronizers • Locally-delayed clocks • Analysis

3. A GALS Module contains: Synchronous Island Local clock generator Self-timed wrapper (can stop the local clock) Handshake for inter-modular communications, GALS with Stoppable Clocks Moore et al., “Point to point GALS interconnect,” ASYNC 2002 Villiger et al., “Self- timed Ring for Globally- Asynchronous Locally- Synchronous Systems,” ASYNC 2003

4. Data Synchronization Moore et al., “Point to point GALS interconnect,” ASYNC 2002 Villiger et al., “Self- timed Ring for Globally- Asynchronous Locally- Synchronous Systems,” ASYNC 2003

5. Synchronization Failure Due to clock tree delay, the previous clock rise may conflict with the handshake

6. d Synchronization Failure: RACE ! Conflict Condition: DCLK = d + x

7. Conflict / Safe Zones

8. Three Solutions

9. Solution 1:Timing Verification • Extract delays • Verify that DCLK falls inside the SAFE zones SAFE SAFE … SAFE

10. Solution 1:Matched Delay Port Control

11. Solution 1: Disadvantages • Clock tree delays must be re-verified after each layout iteration • The solution is sensitive to thermal and voltage variations

12. Solution 2:Two-Flop Synchronizer • Low bandwidth • Resolution time: one clock cycle • Data Cycle: At least 3 clock cycles

13. Solution 3:Locally Delayed Latching

14. Solution 3:Time Budget Clock Y MS DCTRL Y1 Conflict Port Wins MS Y1 DCTRL Clock Wins Asynchronous Controller Delay Clock Y1High-Phase MUTEX Metastability Resolution

15. How much resolution time? • Less than 50 FO4 delays needed to resolve metastability • ASIC / SoC clocks are slow: T > 100 FO4 delays • Conclusions: • Fast clocks: Half a cycle is budgeted for M/S resolution • Slower clocks (T>200 FO4): Quarter cycle REQUIRED MTBF (YEARS)

16. Solution 3:Operating Modes

17. Solution 3:A. Decoupled Input Port DCTRL= D{R3+DO+ DI+L-R2-}

18. Solution 3:B. Decoupled Output Port DCTRL= D{A4+ A1+ A3-}

19. Solution 3:C. A Simpler Input Port DCTRL= DLATCH + DTX {ACK+  REQ-}

20. DL Solution 3:Analysis Clock Y MS DCTRL Y1 Conflict Minimal Clock High-Phase, THP ~3 FO4 gate delays T/4 for M/S Resolution Asynchronous Controller Delay • Example: T=160 FO4 gate delays. Constraint:

21. Solution 3:Simulations *These results are based on data bus width of 16 bits

22. Summary • Design of arbitrated clocks for GALS SoCs must consider clock tree delays to control the risk of synchronization failures • Presented three solutions: • Extract the delays and verify timing • Employ 2-flop synchronizers or matched-delay async ports (low bandwidth) • Employ locally-delayed ports(high bandwidth)