ECE 697B (667) Fall 2004 Synthesis and Verification of Digital Circuits

1. ECE 697B (667)Fall 2004Synthesis and Verificationof Digital Circuits Design Styles and Methodologies Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003

2. Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Pre-diffused Pre-wired Ma cro Cells Compiled Cells (Gate Arrays) (FPGA's) Implementation Choices

3. The Custom Approach Intel 4004 Courtesy Intel

4. Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8486 Intel 8286 Transition to Automation and Regular Structures Courtesy Intel

5. Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers

6. Standard Cell — Example [Brodersen92]

7. Standard Cell – The New Generation Cell-structure hidden underinterconnect layers

8. Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

9. Automatic Cell Generation Initial transistor geometries Placedtransistors Routedcell Compactedcell Finished cell Courtesy Acadabra

10. Product terms x x 0 1 x 2 AND OR plane plane f f 0 1 x x x 0 1 2 A Historical Perspective: the PLA

11. Two-Level Logic Every logic function can beexpressed in sum-of-productsformat (AND-OR) minterm Inverting format (NOR-NOR) more effective

12. Programmable Logic Array Pseudo-NMOS PLA V DD GND GND GND GND GND GND GND V X X X X X X f f 0 0 1 1 2 2 0 1 DD AND-plane OR-plane

13. Dynamic PLA f AND V GND DD f OR f OR f AND V f f GND X X X X X X 0 1 0 0 1 1 2 2 DD AND-plane OR-plane

14. Or-Plane And-Plane V f GND DD PLA Layout – Exploiting Regularity

15. Breathing Some New Life in PLAs River PLAs • A cascade of multiple-outputPLAs. • Adjacent PLAs are connected via river routing. • No placement and routing needed. • Output buffers and the input buffers of the next stage are shared. Courtesy B. Brayton

16. Experimental Results Area: RPLAs (2 layers) 1.23 SCs (3 layers) - 1.00, NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R. Also: RPLAs are regular and predictable Layout of C2670 Standard cell, 2 layers channel routing Standard cell, 3 layers OTC Network of PLAs, 4 layers OTC River PLA, 2 layers no additional routing

17. MacroModules 25632 (or 8192 bit) SRAM Generated by hard-macro module generator

18. “Soft” MacroModules Synopsys DesignCompiler

19. “Intellectual Property” A Protocol Processor for Wireless

20. Design Capture Behavioral HDL Pre-Layout Simulation Structural Logic Synthesis Floorplanning Post-Layout Simulation Placement Physical Circuit Extraction Routing Tape-out Semicustom Design Flow Design Iteration

21. The “Design Closure” Problem Iterative Removal of Timing Violations (white lines) Courtesy Synopsys

22. Integrating Synthesis with Physical Design RTL (Timing) Constraints Physical Synthesis Macromodules Fixed netlists Netlist with Place-and-Route Info Place-and-RouteOptimization Artwork