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Robust Adaptive Topology Control ARPA-E Quarter 4 Review May 23, 2013. RATC Algorithm Team – Work Plan. Economic RATC: UCB 1.4, 1.11 Corrective RATC: ASU (majority) and TAMU (Erick) 1.4, 1.12, 2.1 Parallelization: ASU, TAMU, UCB, and LLNL (Kory, Erick, Shmuel, Barry) 1.6
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Robust Adaptive Topology Control ARPA-E Quarter 4 Review May 23, 2013
RATC Algorithm Team – Work Plan • Economic RATC: UCB • 1.4, 1.11 • Corrective RATC: ASU (majority) and TAMU (Erick) • 1.4, 1.12, 2.1 • Parallelization: ASU, TAMU, UCB, and LLNL (Kory, Erick, Shmuel, Barry) • 1.6 • AC Feasibility: ASU, TAMU, UCB (Kory, Shmuel, Garng) • 1.9, 1.11, 1.12 • Stability: TAMU (Garng) • 1.9, 1.11, 1.12
Feedback from prior report • Collaboration across the algorithm team • Common test cases • Market related issues • Motivation of a market design and structure • Winners and losers • FTRs
Overview of Milestones and Deliverables • Remaining tasks for Go-No-Go Task 1.12: • Additional AC studies (for IEEE 73 bus test case); additional stability studies • Remaining tasks for Task 2.1 (due 9/30/2013): • Simulations complete; Need avoided costs numbers (there are different ways to calculate avoided costs; if we use Value of Lost Load, then the task is 100% complete)
Task 1.4 Greedy Algorithm (Corrective RATC) All requirements associated to Task 1.4 were previously reported and all tasks are completed
Task 1.6 Parallelization of the Greedy Algorithm (Corrective RATC)
Real-time Corrective RATC – Parallelization results via LLNL Results satisfy Task 1.6 and are a part of the results for 1.12
Real-Time Sequential and Parallel GA Results Optimality Gap is 6% (<25%); more info on slide 24 • Parallel processing is tested on the IEEE 118v2 with 103% loading condition • All results belong to the G-2 contingency • The results are for 186 nodes Parallelization results presented only for the IEEE 118 test case
Computational Performance vs. Number of Nodes (Greedy Algorithm Corrective RATC) • Tasks per node indicates the number of cores in one node node
Day-ahead Corrective RATC – Parallelization results at ASU Results satisfy Task 1.6 and are a part of the results for 1.12
Day-Ahead Parallel vs. Sequential Greedy Algorithm Parallel Sequential
Day-Ahead Parallel vs. Sequential Greedy Algorithm • The sequential greedy algorithm performs well in Day-Ahead application in IEEE 118 Bus test case. This means that the average number of evaluations for each switching action is around 1.5. • Thus, parallelization of the algorithm does not significantly improve the computational time. • In the case with larger length of the rank list, parallel greedy may take longer than the sequential algorithm. • Since the parallel algorithm tests all the candidates in the list, the load shed reduction is larger on average with the parallel algorithm.
Day-Ahead Parallel vs. Sequential Greedy Algorithm- Full Comparison
Prior work on parallelization of greedy algorithm (corrective RATC) • Nothing New work on parallelization of greedy algorithm (corrective RATC) • Real-time simulation: • Parallelization is done for G-2 contingencies for the 118v2 test case for 103% loading condition • The performance is checked by varying the number of nodes • Day-ahead corrective: • Implement RATC inside contingency analysis • Parallelization; sensitivity regarding number of switching actions and allowable depth in the priority list (priority list is truncated to include only limited potential switching actions)
Greedy Algorithm, MIP Heuristic, and traditional MIP for N-1 (Day-Ahead) IEEE 118 test case results presented; IEEE 73 test case results will be in report
Prior work on Day-ahead N-1 Corrective RATC • Nothing reported New work on Day-ahead N-1 Corrective RATC • The methodology has been developed; results are analyzed for the 118-bus test system. • All metrics for Go-No-Go have been reported and met (except for AC feasibility and stability)
Real-time Corrective RATC: N-1 and N-2 Events Results pertain to both Task 1.12 and Task 2.1
Test Scenario – (N-1 and N-2) • The greedy algorithm is implemented and tested on the 118 and 73 bus test systems (both versions) • The contingencies for which the initial 10 minute generation ramp rate alone is insufficient to avoid load shedding are termed as non trivial cases • The improved capability to serve load with switching is analyzed • Results show substantial potential to recover from contingencies with transmission switching
Results for N-1 Contingencies • There were no non-trivial cases for N-1 with the 73 bus test case both versions • Results are based on a restriction on search limit of 6 per iteration (for finding a beneficial action)
Results for N-2 Contingencies • Results are based on a restriction on search limit of 6 per iteration (for finding a beneficial action)
Traditional CPLEX and Greedy Algorithm Results • The traditional CPLEX has a 60 minute ramping limit and unlimited switching • IEEE 73 bus test case is not 2x faster than traditional CPLEX
Increase in Number of Contingencies without Load Shedding Results for 103% will be in the report
Prior work on N-m Corrective RATC • Results for N-1 events • Results for G-2 and T-2 events New work on N-m Corrective RATC • Results for N-2 events • Comparison of the greedy algorithm results with the traditional CPLEX • All metrics for Go-No-Go have been reported and met (except for AC feasibility and stability)
AC Feasibility • Unit commitment and N-1 reliability study are based on DCOPF • AC feasibility can be achieved by turning additional units ON • Out-of-market correction increases operational cost by 11% 28
AC Feasibility Similar results will be reported in the progress report
Prior work on AC feasibility (greedy algorithm corrective RATC) • Nothing New work on AC feasibility (greedy algorithm corrective RATC) • Developed an AC feasible test cases • Analyzed the effect of transmission switching on AC feasibility for N-1 events (Day-Ahead) • All metrics for Go-No-Go have been reported and met (for N-1 events – Corrective RATC) • We have not tested AC feasibility for all simulations but a subset
Test Case and Cascading Outage Scenario • Scenarios: • 5 lines have a permanent fault; 15 lines were tripped and are available to be switched back in • 3 lines have a permanent fault; 12 lines were tripped and are available to be switched back in • Conditions: • Only lines that were tripped can be switched back to service. Lines in service cannot be switched • All lines without a permanent fault can be switched
Fault on 3 lines without switching restrictions • Results are based on a restriction on search limit of 4per iteration (for finding a beneficial action)
Fault on 5 lines without switching restrictions • Results are based on a restriction on search limit of 4per iteration (for finding a beneficial action)
Load Shed Recovery from Cascading Events – The Greedy Algorithm versus the Traditional MIP GRDO – generation re-dispatch without switching GASL16 – greedy algorithm with a restriction on search limit of 16 per iteration (for finding a beneficial action) • Not all contingencies gave a solution within a reasonable time frame for the traditional MIP • Results are analyzed for 63 contingencies with a fault on 1 line and 2 generators • The MIP gap for the traditional MIP was set to 0.5% (no limit on ramping and switching) • Task 2.1 metric: 2x faster than traditional MIP is achieved for the IEEE 118 test case
Prior work on Cascading Events - Corrective RATC • 5 lines with permanent faults (lines 1-5, test case 73-bus v1) • 21 lines were tripped (16 lines were tripped but do not have faults: 6-21) New work on Cascading Events - Corrective RATC • 33 cases with a fault on 5 lines, 58 cases with a fault on 3 lines - IEEE 118 v1, IEEE 118v2 test case with 100 and 103% loading conditions were tested • 14 cases with a fault on 5 lines, 35 cases with a fault on 3 lines - IEEE 73 v1, IEEE 73v2 test case with 100 and 103% loading conditions were tested • All metrics for Go-No-Go have been reported and met
Summary • Substantial reduction in load shed is achieved with transmission switching on all cases tested • The greedy algorithm provides more than 5 times faster results as compared the traditional CPLEX for an optimality gap of less than 25% • For real-time application greedy algorithm requires 30% of the switching actions as compared with the traditional CPLEX • Parallelization of the greedy algorithm provides speed up factors of up to 7 times as compared to the sequential greedy algorithm version (sequential greedy algorithm was, on average, at least 6 times faster) • The greedy algorithm is implemented and a subset of the solutions have been checked for AC feasibility
Summary • All the requirements for tasks 1.4 and 1.6 are satisfied • Minor tasks remain to complete Task 1.12 (Go-No-Go) • Minor tasks remain to complete Task 2.1 (due 9/30/13)
Remaining Go-No-Go work to be completed • AC feasibility for real-time, day ahead applications • Stability for real-time, day ahead applications • Cost savings for small scale testing: Normal Next steps • RATC for renewables (wind) for small-scale testing (2.2 and 2.3 due 12/31/13 for both – we will begin this work next) • Initial large-scale testing
Greedy Algorithm Overview • Iterative process • Ranks lines from highest to least likely to provide improvement • Based on a sensitivity study • Sensitivity reflects marginal improvement by switching lines • The solution obtained from greedy algorithm does not have guaranteed feasibility • Multiple solutions are generated in each iteration
Benefits of the Greedy Algorithm • Fast solution time – suitable for real-time application • With one iteration sensitivity of all the lines can be determined • Adaptable to different types of scenarios • Parallelizable
Performance of the Greedy Algorithm with Time • The results include the average over all G-2 contingencies
Fault on 3 lines with switching restrictions • Results are based on a restriction on search limit of 4per iteration (for finding a beneficial action)
Fault on 5 lines with switching restrictions • Results are based on a restriction on search limit of 4per iteration (for finding a beneficial action)