C code organization

1. C code organization CSE 2451 Matt Boggus

2. Topics • C code organization • Linking • Header files • Makefiles

3. #include • #include works with two types of files • Library files • #include <filename> • Local files • #include “filename” • #include “directory/subdirectory/filename” • By convention, the names of the standard library header files end with a .h suffix • Location of library files • /usr/include

4. C code organization

5. Working with multiple files

6. Compiling • The -c option on the gcc command compiles to object code • Then gcc with -o option merges object files into one executable file • Note that “makefunction.h” is only referred to in a #include statement, never in a compilation command

7. Another example – circular #includes main.c #include “a.h” #include “b.h” void main() { a(10); } a.h #include <stdio.h> #include “b.h” void a(intnum) { if(num!= 0) { num = b(num-1); printf(“%i”, num-1); } } b.h #include <stdio.h> #include “a.h” int b(intnum) { if(num!= 0) { num = a(num/2); printf(“%i”, num); return num; } return 0; }

8. Conditional inclusion #ifndef HEADER_FILE_NAME_H_ #define HEADER_FILE_NAME_H_ // contents of header_file_name.h goes here // … #endif

9. Makefile overview • Makefiles are a commonly used tool to handle compilation of large software projects in UNIX • Makefiles contain UNIX commands and will run them in a specified sequence • Mandatory makefile file names: makefile or Makefile • You can only have one makefile per directory • Anything that can be entered at the UNIX command prompt can be in the makefile • Each command must be preceded by a TAB and is immediately followed by a carriage return • To execute, be in the directory where the makefile is: • % make tag-name (also called section name) • examples: • make • make all • make clean

10. Makefile example # this line is a comment all: mainprog mainprog: makefunction.omainprog.o gccmakefunction.omainprog.o -o mainprog makefunction.o: makefunction.c gcc -c makefunction.c mainprog.o: mainprog.c gcc -c mainprog.c clean: rm -rf *.o mainprog

11. Makefile details • We could compile our example like this: • gcc -o mainprogmainprog.cmakefunction.c • But what if we made changes to only makefunction.c? • A makefile is often composed of lines with the following format: • target: dependencies [tab] system command • “all” is the default target for makefiles • all: gcc -o mainprogmainprog.cmakefunction.c • The make utility will execute this target, “all”, if no other one is specified.

12. Makefile dependencies • Useful to use different targets • Because if you modify a single project, you don’t have to recompile everything, only what you modified • In the example makefile: • All has only dependencies, no system commands • For make to execute correctly, it has to meet all the dependencies of the called target • Each of the dependencies are searched through all the targets available and executed if found. • make clean • Get rid of all the object and executable files • Free disk space • Force recompilation of files

13. Additional information on makefiles • http://www.gnu.org/software/make/manual/make.html • Variables in makefiles