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Timing-Driven Synthesis for Fast Barrel Shifters

Timing-Driven Synthesis for Fast Barrel Shifters. Sabyasachi Das University of Colorado, Boulder Sunil P. Khatri Texas A&M University. What is a Shifter?. IC block that performs shifting of data signals Well-known logic architectures Computationally-intensive

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Timing-Driven Synthesis for Fast Barrel Shifters

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  1. Timing-Driven Synthesis for Fast Barrel Shifters Sabyasachi Das University of Colorado, Boulder Sunil P. Khatri Texas A&M University

  2. What is a Shifter? • IC block that performs shifting of data signals • Well-known logic architectures • Computationally-intensive • Occupies significant amount of area • Wide usage in DSP, Graphics, Microprocessors

  3. Introduction to Barrel Shifter • Widely used Shifter architecture • Exhibits good timing characteristic • Area-efficient as well • Inherent regularity in physical structure

  4. Structure of Barrel Shifter • Width of input and output data signals = n bits • Width of input shift signal = log2n bits • Shifter consists of log2n stages • Each bit of the shift signal controls one stage • Each stage handles single shift of 0 or 2i bits

  5. Example of a Barrel Shifter (2-stage) x01’b0 x1 x0 x2 x1 x3 x2 s0 s0 s0 s0 x2 x1 x0 1’b0 1’b0 1’b0 s1 s1 s1 s1 x0 x2 x1 1’b0 z1 z0 z2 z3 S0 = 1’b1 S1 = 1’b0

  6. xaxbxc xd si sj zij Proposed Dual-Merged Stage • Merge stages i and j • 4 bit input data signal • 2 bit shift signal • i and j do not need to be two consecutive bits of the shift signal

  7. Proposed Dual-Merged Stage • For the qth BitSlice (Column) of a left shifter • xa = xq • xb = x(q-2i) • xc = x(q-2j) • xd = x(q-2i-2j) • For the qth BitSlice (Column) of a right shifter • xa = xq • xb = x(q+2i) • xc = x(q+2j) • xc = x(q+2i+2j)

  8. x3 x2x1x0 x2 x1x00 x1 x00 0 x00 0 0 s0 s0 s0 s0 s1 s1 s1 s1 z3 z2 z1 z0 Example of a 2-Stage Shifter Using Dual-Merged Stages x2 x1 x0 1’b0 S1S0 = 2’b01

  9. xexfxg xh xaxb xc xd si sj sk zijk Proposed Triple-Merged Stage • Merge stages i, j and k • 8 bit input data signal • 3 bit shift signal • i, j and k do not need to be three consecutive bits of the shift signal

  10. Triple-Merged Stages • For the qth BitSlice (Column) of a left shifter • xa = xq • xb = x(q-2i) • xc = x(q-2j) • xd = x(q-2k) • xe = x(q-2i-2j) • xf = x(q-2i-2k) • xg = x(q-2j-2k) • xh = x(q-2i-2j-2k)

  11. Identification of Mergeable Stages • Timing-driven algorithm • Uses arrival-time of the shift signals • Uses the timing characteristic of the technology library cells

  12. Algorithm to Find Mergeable Stages • Sort shift signals by arrival time (Si, Sj, Sk are earliest) • Analyze dual-merged stage, triple-merged stage and unmerged stage to decide whether • To create a triple-merged stage by merging stages i, j and k • To create a dual-merged stage by merging stages i and j • To create an unmerged stage for the stage i • Continue analysis with the next three stages corresponding to the 3 earliest arriving shift bits.

  13. Analysis of an Unmerged Stage xa xb • Compute the impact of an unmerged stage (i) • Tsingle = Arr_T (si) + Del1 si Arr_T(si) xc Tsingle Arr_T(sj) sj xd sk Arr_T(sk)

  14. Analysis of Two Unmerged Stages xa xb • Compute the impact of 2 cascaded unmerged stages • Tsingle2 = Max (Tsingle, Arr_T (sj)) + Del1 si Arr_T(si) xc Arr_T(sj) sj xd Tsingle2 sk Arr_T(sk)

  15. Analysis of Three Unmerged Stages xa xb • Compute the impact of 3 cascaded unmerged stages • Tsingle3 = Max (Tsingle2, Arr_T (sk)) + Del1 si Arr_T(si) xc Arr_T(sj) sj xd sk Arr_T(sk) Tsingle3

  16. xaxbxc xd si sj zij Analysis of a Dual-merged Stage • Compute the impact of a dual-merged stage (i, j) • Tdual = Arr_T (sj) + Del2 Arr_T(si) Arr_T(sj) Tdual

  17. xexfxg xh xaxb xc xd si sj sk zijk Analysis of a Triple-merged Stage • Compute the impact of a triple-merged stage (i, j, k) • Ttriple = Arr_T (sk) + Del3 Arr_T(si) Arr_T(sj) Arr_T(sk) Ttriple

  18. Selection of Mergeable Stages • If (Ttriple<Tsingle3) and (Ttriple<(Tdual + Del1/2)) • Implement triple-merged stage (for stages i, j and k) • Else if (Tdual<Tsingle2) • Implement dual-merged stage (for stages i and j) • Else • Implement single unmerged stage for stage i

  19. Results On an average, 10.19%faster than the result of the commercial Datapath Synthesis tool

  20. Summary • Merge 2 stages to form Dual-Merged stage • Merge 3 stages to form Triple-Merged stage • Timing-driven algorithm to identify mergeable stages • Reduces the number of stages upto one-third (33.33%) • On an average, 10.19% faster

  21. Thank you

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