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System Architecture for On-Chip Networks

System Architecture for On-Chip Networks. Jose Duato, Partha Kandu, Manolis Katevenis, Chita Das, Sudhakar Yalamanchili, John Lockwood, Ani Vaidya. Summary. Societal Impact Lower NRE costs (integration and verification): lower barrier to entry

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System Architecture for On-Chip Networks

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  1. System Architecture for On-Chip Networks Jose Duato, Partha Kandu, Manolis Katevenis, Chita Das, Sudhakar Yalamanchili, John Lockwood, Ani Vaidya

  2. Summary Societal Impact • Lower NRE costs (integration and verification): lower barrier to entry • Enable new powerful edge-devices with applications to health care, communication, personalized services • OCIN can help cost effectiveness of the business enterprise and integration in Grid environments • Simplify configuration management of partitionable systems • Application requirements : Performance, Partitioning, QoS • Support for virtualization • Support for heterogeneity • Technology constraints : Power consumption, Temperature, Area, Fault tolerance • Self configuring systems (self healing, self adaptive) • Complexity/Productivity • Profiling, monitoring, debugging support • Software driven adaptation : active topology, routing and load balancing

  3. Sample Research Agenda • Congestion control with bounded or limited buffering • Efficient buffering and flow control • Network interface • Light weight, generic: low latency, tightly coupled, general programming, flexible and general purpose • Virtualized network interface • Adaptive flow control/ switching for multi-modal traffic and time varying application requirements                        • Automatic reconfiguration in the middle of failure • Self tuning links and switches to process variation, soft errors • Network reconfiguration to adapt to application requirements • Support for out of order delivery • Technology-aware topologies : higher dimensions • Support for partitioning and virtualization: isolation, performance across domains, accelerators, traffic heterogeneity • Support for monitoring, debugging

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