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32 BIT PLP MIPS GRADUATE COMPANY

32 BIT PLP MIPS GRADUATE COMPANY (Syed Aleemuddin , Abhishek Divekar , Shalmali Kulkarni, Anuj Kulkarni, Kanishka De, Azharuddin Mohammed , Azher Khan, Rabin Thapa ). Project Overview The implementation of PLP MIPS includes following four phases: 0 . Team building

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32 BIT PLP MIPS GRADUATE COMPANY

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  1. 32 BIT PLP MIPS GRADUATE COMPANY (Syed Aleemuddin, AbhishekDivekar, Shalmali Kulkarni, Anuj Kulkarni, Kanishka De, AzharuddinMohammed , AzherKhan, Rabin Thapa) Project Overview The implementation of PLP MIPS includes following four phases: 0. Team building Research : Information gathering about MIPS processor, building data path for PLP ISA and block diagram Module Implementation : Implementing each module in Verilog Integration : Module Integration and System Testing, Implementation on FPGA • Technical Features • Implements 27 Instructions of PLP ISA • 5 Stage Pipelined Architecture • Hazard Detection and Correction Unit • Flush Logic Background “Max is hungry…!!!” A toaster with PLP MIPS in it comes to the rescue…!!! PLP (i.e.) The Progressive Learning Platform (PLP) utilized on the PLP Board provides a unique learning platform designed to be simple, open, and useful for education. PLP MIPS can replace microcontrollers in applications like Smart Phones, Routers, Robots, Gaming Systems. Functional Block Diagram Additional Information: For more Information on our project visit : code.google.com/p/ecen4243-grad-2013 For complete ISA and reference design visit : plp.okstate.edu Conclusion PLP is an FPGA based computer architecture learning platform which requires us to have a wider scope of computer engineering design principles. This was accomplished with a problem-based curriculum, that includes a projectduring which the team went through each step of design process. Integrating smaller modules leading to the design of complete PLP MIPS CPU.

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