ECE 352 Digital System Fundamentals

1. ECE 352Digital System Fundamentals Prof. Lipasti and Prof. Schulte Week 11

2. Topics • Control units • Algorithmic state machines (ASMs) • ASM charts • Binary multiplication • Hardwired control • Sequence register and decoder • One flip-flop per state method • Microprogrammed control

3. Digital System Control • The binary information stored in a digital system can be broadly classified as either data or control information. • Data processing occurs in the datapath, using microoperations implemented as register transfers. • The control information is used to direct the activities of the datapath circuits to produce the intended results, based on the control state and control inputs.

4. Control Unit • The control unit supervises the overall circuit operation by generating signals that control the register transfer operations. • The control unit can be designed for different types of systems • Programmable systems • A sequence of instructions are stored in memory, and then retrieved and executed by the control unit. • Nonprogrammable systems • The sequence of operations is controlled by the control logic and control inputs only.

5. Algorithmic State Machines (ASMs) • An ASM chart shows both the state sequence and processing actions. • The ASM chart contains essentially the same information as a state diagram for the sequential circuit, and also represents the datapath operations that will occur as a result of control unit outputs. • The ASM chart is constructed from state boxes, decision boxes, and conditional output boxes, linked with directed lines.

6. ASM Chart –State Box • The state box represents a state in the control sequence. • Single entry and exit points. • Labeled with state name and binary code. • Register transfer and signal activations listed inside will occur on each clock pulse while in that state.

7. ASM Chart –Scalar Decision Box • The scalar decision box represents the effect of control inputs. • Single entry and two exits (labeled 0 and 1). • The box lists a single input variable or a boolean expression of just input variables. • The evaluation of the condition determines which path is to be taken.

8. ASM Chart – Conditional Output Box • The conditional output box specifies register transfers or signal activations that are to take place after a specified condition. • Must be placed in a path on the output of one or more decision boxes.

9. ASM Chart –Vector Decision Box • The vector decision box represents the effect of a number of control inputs in a single structure. • Single entry, 2n exits for n-element vector. • Replaces a tree of scalar decision boxes.

10. ASM Chart Timing • State box signal activations and register transfers occur on every clock while in that state, i.e. Moore model circuit. • Conditional output box register transfers occur on the next clock after the condition is true (i.e in the next state), but only occur once. • Conditional output box outputs occur at the same time as the inputs that caused the condition to change, i.e. Mealy model.

11. ASM Chart Exercises • Prepare an ASM chart for • Project 2 CTL module • Frequency counter • fclock = 1Mhz, count for 1ms • BCD combination lock (4 numbers) • Correct key beep • Wrong key time-out (100 clocks)

12. Binary Multiplication • A sequential approach is used to perform the equivalent of hand multiplication. • For each 1 in the multiplier, we add a left-shifted version of the multiplicand. • This allows us to use just one adder and a shift register to accumulate the result as a partial product.

13. Binary Multiplication Hardware

14. Binary Multiplication ASM Chart • Assume that the multiplier and multiplicand are loaded before starting. • How many states are required? • Draw an ASM chart showing: • The required states. • The decisions that are made. • The register transfers that occur.

15. Hardwired Control • When implementing a control unit, we can break the problem into two parts; • the part that determine what happens next. • the part that generates the outputs. • We break the ASM chart into two parts to do this; • A table showing the outputs as a function of state and inputs. • A simplified ASM showing just the state sequence.

16. Binary Multiplier Implementation • What operations are required for the registers in the binary multiplier? • Identify the registers and operations. • Name the control signals that will signal those operations. • Determine the expressions for those control signals as a function of state and inputs. • Revise the ASM diagram to show just the state sequencing information. • Assign binary codes to the states.

17. Hardwired Control Design Methodologies • Sequential logic design process • State table, state diagram, etc. • Sequence register and decoder • Uses a sequence register (counter) and decoder to form signals indicating each state. • One flip-flop per state • aka one-hot controller • One flip-flop is used to represent each state • The current state is represented by a flip-flop with a 1, all other flip-flops are 0.

18. Sequence Register and Decoder • Use an n-bit sequence register for m states (m ≤ 2n). • Use an n-to-2n decoder to provide m signals corresponding to the states. • The control outputs are obtained from the decoder signals and the inputs. • The FF input equations are obtained from the state outputs and inputs, simplifying the work required. • Apply to the multiplier example…

19. One Flip-Flop Per State Method • In this method, a flip-flop is used for each state. • The current state is defined by the flip-flop that contains a 1. • The logic design is usually very simple using this method – one advantage of doing it this way. • The conversion from ASM chart to hardware is very direct.

20. One Flip-Flop Per State Method • Alternatively, the input logic to each flip-flop can be viewed as providing a 1 if and only if • this flip-flop is the current state and no state change will occur, or, • this flip-flop is the next state and a state change will occur. • Apply to the multiplier example…

21. Microprogrammed Control • Control is based on binary values (words) stored in memory. • Each word specifies one or more microinstructions. • A sequence of microinstructions is a microprogram. • The control words are retrieved from control memory by read operations. • Control memory may be writable.

22. Operation • Sequencer • Determines the next control address to read from. • Can go out of sequence in response to inputs. • Control inputs • Datapath status • Next-address info

23. Operation • ROM contains the microprogram. • Control Data Register (CDR) is optional.

24. Wrapping Up • Do the reading for next week! • Textbook 9.1-9.8 • Work on Project 2! • Due Friday 12/9 in class

25. CTL Module • The CTL module provides the overall power-on reset for the other transmitter modules, and then loads data into the FIFO as it becomes available. The FIFO uses the done input to show that it has loaded the data. Your control logic must ensure that the compressed input data is only stored in the FIFO once for each time the dav input is set to 1 (for a given input data word, dav may remain at 1 for more than a single clock cycle). You may assume that dav will be 0 for at least one clock between input data words, and that the input data is valid as long as dav is a 1. If the FIFO is unable to store the incoming data before dav becomes 0, the data is lost. • Inputs • • done (FIFO data storage complete): This is set to 1 to indicate that the FIFO has loaded the data that was presented to it. • • dav (data available): When dav is 1, there is valid data available for transmission. • Outputs • • rst_out (synchronous reset): This output provides a power-on reset to the reset of the circuit. It must be set to 1 at all times while reset is a 1, then remain a 1 for 2 clock periods after reset has gone to 0. • • store (store data in FIFO) : Indicates to the FIFO that there is valid data to be stored. This output must go to 0 as soon as the FIFO indicates it has stored the data (done is a 1) or the input data is not valid (dav has gone to 0).

26. One FF per State ASM

27. One FF per State ASM

28. S