Performed by: Yulia Turovski Lior Bar Lev Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Final Presentation I Subject: High-Speed Communication Channel(s) Switch Performed by: Yulia Turovski Lior Bar Lev Instructor: Mony Orbach Winter semester 2010 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Motivation and Goal • Motivation: • High-speed communication between devices. • Utilizing high frequency achievable with new hardware. • Demand for reliable communication • Goal: • Design & implementation of high speed communication switch. • Use of advanced communication protocols. • Connect between as many devices as possible. • Best transmission rate possible. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Stratix II SI Development Kit 2

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Architecture Diagram ROUTER 128 128 128 ALTGX ALTGX ALTGX TRNS TRNS TRNS OUTBUF OUTBUF OUTBUF 32 32 32 128 ALTGX TRNS OUTBUF 32 INBUF INBUF INBUF INBUF 32 RECV 128 SPLIT INBUF 32 32 32 RECV RECV RECV SPLIT SPLIT SPLIT 128 128 128 INBUF Trans Mem INBUF INBUF INBUF INBUF INBUF INBUF INBUF Trans Mem Trans Mem Trans Mem INBUF INBUF INBUF 3

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Validation Method • 2 transmitters with pre-initialized dual port rams • Simple data validation control (to keep track of number of packets sent) • A few scenarios were implemented - • Measure latency • CRC code detection • Latency is 264 clock cycles = 1.6896 usec • Measure Throughput • Parallel transmission • Output the data through In-Mem interface • Process: force reset down and up, examine output mem. 8

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Under Test Test device Switch Port I Port I Out Mem RT Testbench TRNS RECV Port II Port II Out Mem TRNS RT Testbench RECV Port III Port III TRNS Out Mem RT Testbench RECV Port IV Port IV RT Testbench TRNS Out Mem RECV 2