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Lecture 9 Addendum. FPGA Implementation of Multipliers. Source. Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, . Chapter 12: Multipliers Section 12.1.7 FPGA Implementation of Multipliers.
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Lecture 9 Addendum FPGA Implementation of Multipliers
Source Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, Chapter 12: Multipliers Section 12.1.7 FPGA Implementation of Multipliers
Notation Y Multiplicand yk-1yk-2 . . . y1 y0 X Multiplier xm-1xm-2 . . . x1 x0 P Product (Y X ) pm+k-1pm+k-2 . . . p2 p1 p0 If multiplicand and multiplier are of different sizes, usually multiplier has the smaller size
Xilinx FPGA Implementation Equations Z = (2xm-1+xm-2) Y 2m-2 + … + (2xi+1+xi) Y 2i + … + +(2x3+x2) Y 22 + (2x1+x0) Y 20 (2xi+1+xi) Y = pi(k+1)pikpi(k-1)…pi2pi1pi0 pij = xiyj xor xi+1yj-1 xor cj cj+1 = (xiyj)(xi+1yj-1) + (xiyj)cj + (xi+1yj-1)cj c0 = c1 = 0
Modified Basic Cell Xilinx FPGA Implementation xi+1 xi cj+1 yj yj-1 FA pij cj
Modified Basic Cell Xilinx FPGA Implementation LUT: xiyj xor xi+1yj-1 cj+1 xi yi xi+1 LUT 0 1 yi-1 pij cj pij = xiyj xor xi+1yj-1 xor cj cj+1 = (xiyj)(xi+1yj-1) + (xiyj)cj + (xi+1yj-1)cj
Xilinx FPGA Multiplier
