Quartus II Schematic Design Tutorial

1. Quartus II Schematic Design Tutorial Xiangrong Ma max6@unlv.nevada.edu

2. Design Flow

3. Create Project • Project information • Directory • Project name • Top level name • Device • Select Cyclone • (small & fast for compile)

4. Design Capture • Create a new Schematic File • Add Gates • Add Pins • Check Design

5. Compile(Synthesis & Fit & STA) Fix Errors Check Reports

6. Create test stimulus file • Create a waveform vector File • Add input/output pins(using Node Finder) • Change value for input pins • Keep outputs as “X”

7. Setup Simulation Environment • Right Click on Project, • choose “Settings” • Select “Simulator Setting” • Select input file • Select Simulation mode • Functional • timing

8. Generate Netlist • Functional Simulation • Generate Functional netlist file for simulation • 0 delay, just “functional” • Timing Simulation • After Compilation, timing information was extracted from devices • Wire delay/logic delay information would be used for “back-annotated simulation” • Much more accurate

9. Run Simulation

10. Analysis S=A and B C=A or B Fix errors

11. File extension description .qpf Quatus Project File .qsf Quatus Setting File .vwf Vector Waveform File .bdf Block Design File .rpt Report

12. URLs • https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v72.jsp Quartus II 7.2 Web Edition(sp3)