Problem of Packet Mis-Sequencing in Load Balanced BvN Switches

1. Problem of Packet Mis-Sequencing in Load Balanced BvN Switches Siddhartha Saha ECE 284, Prof Bill Lin

2. Introduction • The current growth in Internet traffic • Increased use of fiber optics technology • Electronic routers in the Internet may very well the bottleneck in future. • Requirements of a Switch: • Scalability, Low hardware complexity, 100% throughput, Low average packet delay, Efficient buffer usage, Guaranteed rate services. Siddhartha Saha, ECE 284, Bill Lin

3. Load Balanced BvN Siddhartha Saha, ECE 284, Bill Lin

4. Load Balanced BvN (Contd…) • Points to remember: • 100 % Throughput, with some mild conditions on the input. • No decision making algorithm, i.e., predetermined arbitration sequence. • Packets may be out of sequence. • No internal speedup is required, the internal connections also operate at rate R (= the incoming rate at each port) Siddhartha Saha, ECE 284, Bill Lin

5. Overview • Review the cause of Mis-sequencing • Solutions Suggested: • Multi-Stage Buffering • 3DQ+FFF • FOFF • Some more thinking.. • Conclusion Siddhartha Saha, ECE 284, Bill Lin

6. 2 1 2 1 1 1 1 N N N Example of Mis-Sequencing External Inputs Internal Inputs External Outputs Load-balancing cyclic shift Switching cyclic shift Siddhartha Saha, ECE 284, Bill Lin

7. General Approaches to the Solution • There are usually two approaches to the sequence problem: • To prevent packets from becoming mis-sequenced anywhere in the router • To bound the amount of mis-sequencing, and use a re-sequencing buffer in the third stage • The following approaches also fall in either of these two category Siddhartha Saha, ECE 284, Bill Lin

8. 1. Multistage Buffering • One quick fix idea: Have a resequencing buffer at the output • Problem: Since the packets are distributed according to the arrival time in the first stage, no bound on the resequencing buffer. • Solution: • Load balance each flow rather than load balancing on only the arrival time • A flow splitter and a load-balancing buffer is added in front of the first stage of original LB BvN switch. Siddhartha Saha, ECE 284, Bill Lin

9. Multistage Buffering [Contd…] Siddhartha Saha, ECE 284, Bill Lin

10. Multistage Buffering [Contd…] • The load-balancing buffer at an input port of the first stage is bounded above by NLmax • The resequencing and output buffer at an output port is bounded above by NMmax • Where: • Lmax is the maximum number of flows at an input port • Mmax is the maximum number of flows at an output port Siddhartha Saha, ECE 284, Bill Lin

11. 2. 3DQ + FFF Approach Siddhartha Saha, ECE 284, Bill Lin

12. External Inputs Internal Inputs External Outputs 2 1 2 1 3 1 1 1 N N N Cyclic Shift Cyclic Shift Intuitive Idea • Idea: • Spread cells evenly across all linecards • Read them in order Siddhartha Saha, ECE 284, Bill Lin

13. External Inputs Internal Inputs External Outputs 1 1 2 1 1 1 2 3 N N N Cyclic Shift Cyclic Shift Intuitive Idea • Idea: • Spread cells evenly across all linecards • Read them in order Siddhartha Saha, ECE 284, Bill Lin

14. t External Inputs Internal Inputs External Outputs 2 1 2 2 1 1 3 3 1 1 1 N N N Cyclic Shift Cyclic Shift First Problem Problem: if two packets don’t arrive consecutively, there may be a hole in the reading sequence Siddhartha Saha, ECE 284, Bill Lin

15. t 3 1 2 Flow Load Balancing Coordination Buffer (VOQ) 1 1 2 1 1 1 2 3 N N N Cyclic Shift Cyclic Shift Coordination Buffer Solution: collect cells from a flow in a coordination buffer, and load-balance them among linecards Siddhartha Saha, ECE 284, Bill Lin

16. t Input 1: Input 2: a b t Flow Load Balancing Coordination Buffer (VOQ) 2 3 1 a b 1 3 1 2 1 1 1 2 N N N Cyclic Shift Cyclic Shift Second Problem Problem: No access to cell 2 because of head-of-line blocking Siddhartha Saha, ECE 284, Bill Lin

17. a b 1 3 2 Expanding VOQ Structure Solution: expand VOQ structure by distinguishing among switch inputs Siddhartha Saha, ECE 284, Bill Lin

18. 3DQ/FFF: • Advantage: • No need for any resequencing buffer at the output. • According to the authors, it is practical to implement. • Disadvantage: • Significant hardware requirement. • 3DQ -> Complex buffer management as N becomes large. Siddhartha Saha, ECE 284, Bill Lin

19. 3. Full Ordered Frame First (FOFF) • Almost similar to 3DQ/FFF architecture (by same authors) • Difference: • Do not need 3D Output Queues • We need a resequencing buffer at the output. • Size of the resequencing buffer is bounded by N2 + 1 Siddhartha Saha, ECE 284, Bill Lin

20. Some more thoughts… • Overview and Intuitive Idea: • Claims: Needing neither 3DQs nor Resequencing buffer at the output. • Requires complex (but efficient) memory management • Requires communication from the second stage to the first stage. Siddhartha Saha, ECE 284, Bill Lin

21. Consider the middle stage as a shared memory matrix. Cijdenotes the column number of the last packet where a packet from i to j has been written in the shared memory. • For next write, we need to have C’ij >= Cij • Value of C need to be sent back to the input. Cij Occupied memory positions for the same VOQ from different inputs Cij Input i 1 VOQ for Output j C’ij 2 C’ij Middle Stage Siddhartha Saha, ECE 284, Bill Lin

22. Claims: • The memory management algorithm can be implemented in O(lg*N) amortized time. • We need to send the value of Cij back to input i after the insertion. • No analytical guarantees on throughput as yet. We need to do some simulation. Siddhartha Saha, ECE 284, Bill Lin

23. Thank you • Q/A ?  Siddhartha Saha, ECE 284, Bill Lin