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Encryption infrastructure on-key

Final Presentation. Encryption infrastructure on-key. Written by: Elkin Aleksey Savi Esacov Advisor: Idan Shmuel Winter 2013/14. Background. Now there are a lot of data encryption systems based on hardware

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Encryption infrastructure on-key

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  1. Final Presentation Encryption infrastructure on-key Written by: Elkin Aleksey Savi Esacov Advisor: Idan Shmuel Winter 2013/14

  2. Background • Now there are a lot of data encryption systems based on hardware • These systems encryption mechanism and control system loose, so there is a dependence and lack of flexibility in the system • Separation of encryption mechanism and the control system will increase the system flexibility • Allow to change the encryption mechanism according to the needs • Allow to make verification separate for each component • Allow to work on control system and encryption mechanism in same time • Now the lab are realizing the encryption and decryption mechanism, which is implanted into the shell we must build

  3. Project purposes • Design universal infrastructure for encryption/decryption system using FPGA • Creation GUI • Design control system for tracking data from PC to a SD card and back through encrypts / decrypts • Learning and experience in a variety of areas : • RealTime controlling system • FPGA • Programming

  4. Milestone goals • Planning and creating an interface between the DE2 Board and SD card • Planning and creating an interface between the DE2 Board and PC • Planning and creating GUI • Integration between parts of the system

  5. Instruments • Hardware • DE2 Board • NIOS II core • DLP • SD card • Software • Quartus II 13.0 • Qsys • Eclipse – Software control system • Active-HDL – Hardware simulation • Matlab - GUI Hardware synthesis

  6. Architecture – High Level NIOS II software controller Controller hardware AVALON BUS SD card DLP Encryption Decryption (optional) GUI Sending data to encrypt Or decryption request PC

  7. GUI for converting files • Converting text file from regular form in .dat file and back

  8. GUI for sending/receiving data

  9. DLP-USB245M

  10. Block diagram STOP and WAIT protocol(40 kB/s) DLP Nios II/e CTRL FIFO-NIOS HARDWARE FIFO IN 8 bits (char)× 8192 SD Card CTRL NIOS-SD CARD SOFTWARE USB protocol(1 MB/s) STOP and WAIT protocol(40 kB/s) CTRL PC(DLB)-FIFO HARDWARE DE BOARD CTRL FIFO-NIOS HARDWARE FIFO OUT 8 bits (char)× 8192 PC

  11. NIOS II Core • Using Level 1 debugger is essential for Eclipse • Nios II/e Core – enough for our needs

  12. Top Level FIFO OUT NIOS-SD CARD FIFO IN DLP-FIFO controller FIFO-NIOS controller

  13. Top Level Compilation result • When Total memory bits exceed 85% Quartusunable to do Place & Route procedure

  14. Results • Maximum possible data file size : 8kb(dictated by the FIFO size) • System speed: 40 kb/s (dictated by the NIOS-SD card interface)

  15. Software verification • Software controller (NIOS-SD card) verification done by using Eclipse console and inspection

  16. Hardware verification • Hardware controller (DLP-FIFO and FIFO-NIOS) verification by simulation using Active-HDL 9.1

  17. Bugs and Notes • NIOS II software tools – Eclipse require simple example to begin to wok • Require Altera package for NIOS-SD card interface • Using custom data transmitter from FPGA to NIOS-SD card for calculation maximum system speed

  18. Summary and Conclusions • The most of the goals were achieved project • Using software make system work slowly • NIOS-SD card interface via software decrease system speed • Our project allow to compare hardware and software development and implementation • Hardware harder to develop but it faster and easier for debugging

  19. Future development recommendation • Advancing GUI • Better interface for the novice user • Real Time file system • Using RS422 instead DLP • Speed improvement • Exchange software controller to hardware controller

  20. Thank you for listening

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