DBEr specifications and ICDs Nov 2009

1. DBEr specificationsand ICDs Nov 2009 Steven Durand presenting for the Electronics Division

2. 2011 Performance Goal • Increase the VLBA bandwidth to 1.024 GHz per IF • Increase sustainable bandwidth by a factor of 32 (4.096 Gbits/s data) • Increase sensitivity a factor of 5.7 (8Hr synthesis, X-band, ~10µJy/beam) • Modifications to the existing LO/IF system required

4. Anti-aliasing Filters • 15 dB (relative to maximum response) insertion loss frequencies ….Low: 512 MHz+/-5 High: 1024 MHz+/-5  • 1 dB (relative to maximum response) insertion loss frequencies…. 578 MHz to 958 MHz • Return Loss, 578 to 958 MHz greater than 15 dB • Passband amplitude variation 578 to 958 MHz (slope, taper)…less than 1.0 dB  • Passband amplitude ripple 662 to 874MHz….less than 0.2 dB peak-peak

5. Anti-aliasing Filters

6. Gain Attenuation ICD

7. Gain Attenuation IC

8. ICD TIMING BOARD OUTPUT FREQUENCY RANGE OF THE VLBA DBE TIMING BOARD Low Band 952 – 1137 MHZ High Band 1904 – 2274 MHZ 1PPS OUTPUT OF THE VLBA DBE TIMING BOARD Pulse Width: 20 ms Pulse Polarity: Positive

9. ICD TIMING BOARD A National Semiconductor LMX2531LQ2080E Frequency Synthesizer chip is utilized to produce the timing signal, which can be set at 1 GHZ or 2 GHZ. This chip has a number of registers that must be configured at power-up. A Xilinx Spartan 3AN FPGA communicates with the Frequency Synthesizer via SPI (Serial Peripheral Interface). The FPGA can be programmed to automatically set up the Frequency can pass SPI signals between it and the ROACH board. Synthesizer upon power up, or it The Timing Board synchronizes to the station 1PPS at power-up. After this synchronization takes place, a pulse is issued once per second. A counter derived from the synthesized frequency generates the 1PPS. A check will be done once per second to determine the time interval between the station 1PPS and the 1PPS generated by the timing board. The control computer can check this time interval to be sure that the 1PPS issued by the Timing Board is synchronized with the station 1PPS.

10. Project Book Chapter 3The Digital Backend System (Version 6.2) Updates by Walter Brisken October 16, 2009 Updates by Steven Durand February 11, 2009 Updates by Steven Durand September 19, 2008 Updates by Steven Durand July 29, 2008 Updates by Steven Durand Jan 11, 2008 Updates by Craig Walker Feb 26, 2007 Updates from Haystack Observatory Jan 18, 2007

11. Switched Power Detectors • The specifications for the switched power detectors are as follows: • Accumulation Interval 1 second • Tsys precision in 1 second (for wide bands) 2% (0.5 dB) • Useful range of Tsys (>1 GHz frequencies) 10K to 400K • Tsys linearity over useful range 1% • Number of power detectors (required) 1 per recorded baseband channel • Number of power detectors (goal) 1 per baseband + 1 per 128 MHz sub-band • Data products per power detector Pon, Poff • Effective number of bits per data product 12 • Data completeness (required) >~50% (see note below) • Data completeness (goal) 100%

12. Digital State Counts • VLBI makes critical use of data quantization (typically to 1 or 2 bits per sample) in order to minimize data transmission costs. In order to both minimize unneeded data degradation and in order to properly correct correlator products for the effects of the quantization, the quantizers must have their thresholds set properly and measured frequently. In the case of 1-and 2-bit quantization it makes sense to determine and store the full probabilities of each quantization state as there are only 2 and 4 of these respectively. For more than 2-bits quantization the need to precisely know the distribution is less and the desire to cope with up to 256 values (for 8-bit sampling) is diminished. Thus two statistics should be recorded instead, the mean and root-mean-square (RMS) of the quantized values. • Specifications for the RDBE state occupation counters are: • Accumulation Interval (at VSI-S interface) 1 second • Number of counters 1 per recorded baseband • 1-bit data products P0, P1 • 2-bit data products P00, P01, P10, P11 • > 2-bit data products mean, RMS • Effective number of bits for each product 8 • Data completeness >1% • Note that in contrast to the PCAL and power detectors, precision is not dominated by the statistics of the signals, so the needs of these counters can be met by investigating a very small fraction of the data, if that simplifies the design.

13. Thank You

14. Roach Bd. V-1 Electro-Static Discharge Prevention Program

15. Prototype Roach Board • Verified design and layout • Includes the power PC • Vertex5 -LX110T

16. Two Story Roach Hotel • Enclosure Star USA D107-1.3U • $150US • Power Supply Sun Power SPX-6200A1 • $60US • 200Watt

17. VLBA Antenna • 25 meter dish • Weighs 240 tons • From Mauna Kea on the Big Island of Hawaii to St. Croix in the U.S. Virgin Islands, the VLBA spans more than 5,000 miles, • Dedicated in 1993 • Back End upgrade scheduled - 2009

18. VBDE Clock Board Designed by MIT Haystack

19. VLBA Configuration

20. Control building maser room • 20 dB shielding • Coax cables (4) • Replace present formatter, BBCs and samplers

21. System Configuration

22. FPGA Code • Multiple personalities • Polyphase filters • 8,16,or 32 sub-channels • Digital down converters (4 per roach) • Bandwidth: 62.5 kHz – 256 MHz, in binary steps • Monitor and Control • Phase calibration & State counts • Recorder interface