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A Design Technique for Energy Reduction in NORA CMOS Logic

A Design Technique for Energy Reduction in NORA CMOS Logic. Konstantinos Limniotis, Yiorgos Tsiatouhas , Member, IEEE, Themistoklis Haniotakis , Member , IEEE, and Angela Arapoyanni , Member , IEEE. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS

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Nora logic - PowerPoint PPT Presentation

A Design Technique for Energy Reduction in NORA CMOS Logic