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STT-RAM Circuit Design

STT-RAM Circuit Design. STT-RAM Cell & Column Circuitry Fengbo. 08/23/2010. STT-RAM CELL (2 finger device). Source contacts are shared by the same column Gate contacts are shared by the same row No need to share SL Min. cell size: 27.75 F 2 (W/L = 750/50 nm).

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STT-RAM Circuit Design

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  1. STT-RAM Circuit Design STT-RAM Cell & Column Circuitry Fengbo 08/23/2010

  2. STT-RAM CELL (2 finger device) • Source contacts are shared by the same column • Gate contacts are shared by the same row • No need to share SL • Min. cell size: 27.75 F2 (W/L = 750/50 nm) Wc Depends on W of transistor M4 Hc = 0.5 um

  3. Cell Size v.s. Write Current • Wc = Wgate / 2 + 0.18 um • Will build min. size (27.75), 35, 50 F2 cell in the tapeout 5 ns Switching [J.P. Wang] 3 ns Switching [J.P. Wang]

  4. Column Circuitry • 4.84 x 120 um • 8-1 Mux • 1.5v device induces 4x area overhead incolumn mux and write circuit • For same amount of writing current, same pitch(256 rows each memory core) • Non-boosted case • Memory core height: 405 um • Column circuit height: 48.75 um • Total: 453.75 um • Boosted case with medium oxide device (Our design) • Memory core height: 256 um (63%) • Column circuit height: 120 um (246%) • Total: 376 um • Boosted case with thin oxide device (assume it works) • Memory core height: 256 um • Column circuit height: 48.75 um • Total:304.75

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