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Topic 4 Field-Effect Transistors

ECE 271 Electronic Circuits I. Topic 4 Field-Effect Transistors. Chapter Goals. Describe structure and operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i -v characteristics of MOSFETs.

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Topic 4 Field-Effect Transistors

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  1. ECE 271 Electronic Circuits I Topic 4Field-Effect Transistors NJIT ECE271 Dr. Serhiy Levkov

  2. Chapter Goals • Describe structure and operation of MOSFETs. • Define FET characteristics in operation regions of cutoff, triode and saturation. • Develop mathematical models for i-v characteristics of MOSFETs. • Introduce graphical representations for output and transfer characteristic descriptions of electron devices. • Define and contrast characteristics of enhancement-mode and depletion-mode FETs. • Define symbols to represent FETs in circuit schematics. • Investigate circuits that bias transistors into different operating regions. • Explore FET modeling in SPICE. NJIT ECE271 Dr. Serhiy Levkov

  3. Intro (1) • Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices: NJIT ECE271 Dr. Serhiy Levkov

  4. Intro (1) • Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices: - amplifications (in analog) NJIT ECE271 Dr. Serhiy Levkov

  5. Intro (1) • Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) NJIT ECE271 Dr. Serhiy Levkov

  6. Intro (1) • Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) • There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor). NJIT ECE271 Dr. Serhiy Levkov

  7. Intro (1) • Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) • There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor). • FET: electric field is used to control the shape and the conductivity of the channel of one type charge carrier (p or n) in semiconductor device. • They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT). NJIT ECE271 Dr. Serhiy Levkov

  8. Intro (1) • Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) • There are two basic types of solid state transistors BJT (bipolar junction transistor) and FET (field effect transistor). • FET: electric filed is used to control the shape and hence the conductivity of the channel of one type charge carrier (p or n) in semiconductor device. • They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT). • FET can be of two major types MOSFET (metal oxide semiconductor field effect transistor (mostly used)), and JFET (junction field effect transistor). NJIT ECE271 Dr. Serhiy Levkov

  9. Intro (2) • Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later. • Today, the CMOS technology based on MOSFET is the dominant technology in electronics. NJIT ECE271 Dr. Serhiy Levkov

  10. Intro (2) • Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later. • Today, the CMOS technology based on MOSFET is the dominant technology in electronics. • BJT devices were first introduced in 1948 and quickly became commercially available. The first IC with logic gates and operational amplifiers that appeared in early 1960s, were based on BJT technology. They are still widely used, particularly in applications requiring high speed and high precision. • BJT device is based on pn-junction structure, while MOSFET is utilizing the MOS capacitor structure. NJIT ECE271 Dr. Serhiy Levkov

  11. Metal Oxide Semiconductor Field-Effect Transistors (MOSFET) NJIT ECE271 Dr. Serhiy Levkov

  12. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. NJIT ECE271 Dr. Serhiy Levkov

  13. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. • Consists of two electrodes and insulator in between. NJIT ECE271 Dr. Serhiy Levkov

  14. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. • Consists of two electrodes and insulator in between. • First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. NJIT ECE271 Dr. Serhiy Levkov

  15. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. • Consists of two electrodes and insulator in between. • First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. • Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. NJIT ECE271 Dr. Serhiy Levkov

  16. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. • Consists of two electrodes and insulator in between. • First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. • Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. • Second electrode (Substrate, Body): n- or p-type semiconductor. NJIT ECE271 Dr. Serhiy Levkov

  17. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. • Consists of two electrodes and insulator in between. • First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. • Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. • Second electrode (Substrate, Body): n- or p-type semiconductor. • The semiconductor body has limited supply of holes and electrons, and substantial resistivity. NJIT ECE271 Dr. Serhiy Levkov

  18. MOS Capacitor Structure • Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. • Consists of two electrodes and insulator in between. • First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. • Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. • Second electrode (Substrate, Body): n- or p-type semiconductor. • The semiconductor body has limited supply of holes and electrons, and substantial resistivity. The concentration of carriers being dependant on voltage, the capacitance of this structure therefore is a nonlinear function of voltage applied. NJIT ECE271 Dr. Serhiy Levkov

  19. Substrate Conditions for Different Biases We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form. • Accumulation : VG<<VTN The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) NJIT ECE271 Dr. Serhiy Levkov

  20. Substrate Conditions for Different Biases We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form. • Accumulation : VG<<VTN ,VG<0 The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) • Depletion: 0<VG<VTN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms NJIT ECE271 Dr. Serhiy Levkov

  21. Substrate Conditions for Different Biases We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form. • Accumulation : VG<<VTN The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) • Depletion: 0<VG<VTN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms • Inversion: VG>VTNThe larger positive charge of the gate attracts electrons whose concentration in the very thin layer exceeds that of holes – inversion of p-type into n-type. NJIT ECE271 Dr. Serhiy Levkov

  22. Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate • MOS capacitance is non-linear function of voltage. • Total capacitance in any region is dictated by the separation between capacitor plates. • Total capacitance can be modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance. NJIT ECE271 Dr. Serhiy Levkov

  23. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. NJIT ECE271 Dr. Serhiy Levkov

  24. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) NJIT ECE271 Dr. Serhiy Levkov

  25. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) Drain(D) NJIT ECE271 Dr. Serhiy Levkov

  26. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) Drain(D), Source(S) NJIT ECE271 Dr. Serhiy Levkov

  27. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) Drain(D), Source(S) Body(B) NJIT ECE271 Dr. Serhiy Levkov

  28. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) Drain(D), Source(S) Body(B). • Source and drain regions form pn junctions with substrate. NJIT ECE271 Dr. Serhiy Levkov

  29. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) Drain(D), Source(S) Body(B). • Source and drain regions form pn junctions with substrate. • vSB,= vS – vB, vDS = vD - vSandvGS = vG - vSare typically nonnegative during normal operation. NJIT ECE271 Dr. Serhiy Levkov

  30. NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. • 4 device terminals: Gate(G) Drain(D), Source(S) Body(B). • Source and drain regions form pn junctions with substrate. • vSB,= vS – vB, vDS = vD - vSandvGS = vG - vSare always positive during normal operation. • vB <= vD and vB <= vS , to keep pn junctions reverse biased. NJIT ECE271 Dr. Serhiy Levkov

  31. NMOS Transistor and Variable Resistor • A transistor is a three (or four) terminal device, in which one terminal controls the voltage or current between other two terminals • In certain way it is similar to a variable resistor, in which the movement of the middle terminal controls the voltage. + + - - NJIT ECE271 Dr. Serhiy Levkov

  32. NMOS Transistor: Qualitative Behavior @ vDS =0 • VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. NJIT ECE271 Dr. Serhiy Levkov

  33. NMOS Transistor: Qualitative Behavior @ vDS =0 • VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. • VGS<VTN (VGS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. NJIT ECE271 Dr. Serhiy Levkov

  34. NMOS Transistor: Qualitative Behavior @ vDS =0 • VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. • VGS<VTN (VGS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. • VGS>VTN: Channel is formed between source and drain by electrons in inversion layer. If VDS>0, finite iD flows from drain to source. • iB=0 andiG=0. NJIT ECE271 Dr. Serhiy Levkov

  35. NMOS Transistor: Qualitative Behavior @ vDS =0 Since the induced inversion layer is formed by electrons, it’s called N-channel MOSFET. NJIT ECE271 Dr. Serhiy Levkov

  36. NMOS Transistor: Triode Region Applying a small vDScreates a flow of electrons in the induced inversion layer between source and drain - current iD (iD=iS, since iB=0andiG=0). for where Kn= Kn’W/L – the gain factor Kn’=mnCox’’ (A/V2) Cox’’=ox/Tox ox= oxide permittivity (F/cm) Tox= oxide thickness (cm) This is the triode region (linear region, ohmicmode). MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. NJIT ECE271 Dr. Serhiy Levkov

  37. N-MOS Transistor: Triode Region(derivation of the source-drain current) Since currents iB and iG both are zero, and there is no path for drain current to escape: iS=iD. To find it, we consider the transport of the charge. The linear density of the electron charge at any point in the channel is: The voltage vox is the function of position x in the channel: . For inversion layer to exist, should be vox > VTN , so Q’ = 0 until vox > VTN . At the source, vox = vGSand it decrease to vox = vGS- vDS at the drain. The electron drift current is : , where Combining everything: and integrating: , we get NJIT ECE271 Dr. Serhiy Levkov

  38. Triode (a bit of history) A triode is an electronic amplification device having three active electrodes. most commonly it’s a vacuum tube with three elements: the filament (cathode), the  grid (controlling element), and the plate or anode. The triode vacuum tube was the first electronic amplification device. It’s iv-characteristics was quite linear. NJIT ECE271 Dr. Serhiy Levkov

  39. N-MOSFET: Triode Region Characteristics • The expression for iDis quadratic invDS NJIT ECE271 Dr. Serhiy Levkov

  40. N-MOSFET: Triode Region Characteristics • The expression for iDis quadratic invDSwith max reached at vDS= vGS - vTN = vOV vDS NJIT ECE271 Dr. Serhiy Levkov

  41. N-MOSFET: Triode Region Characteristics • The expression for iDis quadratic invDSwith max reached at vDS= vGS - vTN = vOV • For small vDS<< vGS - vTN, the characteristics iDvs. vDSappear to be linear (triode region, linear) vDS NJIT ECE271 Dr. Serhiy Levkov

  42. N-MOSFET: Triode Region Characteristics • The expression for iDis quadratic invDSwith max reached at vDS= vGS - vTN = vOV • For small vDS<< vGS - vTN, the characteristics iDvs. vDSappear to be linear (triode region, linear) Under this condition, MOSFET behaves like a gate-source voltage-controlled resistor between source and drain, NJIT ECE271 Dr. Serhiy Levkov

  43. N-MOSFET: Triode Region Characteristics • The expression for iDis quadratic invDSwith max reached at vDS= vGS - vTN = vOV • For small vDS<< vGS - vTN, the characteristics iDvs. vDSappear to be linear (triode region, linear) Under this condition, MOSFET behaves like a gate-source voltage-controlled resistor between source and drain, where on-resistance: NJIT ECE271 Dr. Serhiy Levkov

  44. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator NJIT ECE271 Dr. Serhiy Levkov

  45. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator NJIT ECE271 Dr. Serhiy Levkov

  46. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator NJIT ECE271 Dr. Serhiy Levkov

  47. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: NJIT ECE271 Dr. Serhiy Levkov

  48. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: NJIT ECE271 Dr. Serhiy Levkov

  49. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: NJIT ECE271 Dr. Serhiy Levkov

  50. MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: To maintain triode region operation, or NJIT ECE271 Dr. Serhiy Levkov

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