2005 Spring ITRS Workshop : Test TWG

1. 2005 Spring ITRS Workshop :Test TWG April 2005 Munich, Germany

2. Roadmap Update / Plans • 2004 Updates • Minor changes to most tables • 2005 Revision • Reliability Screens update • Consolidation of various logic ATE/product tables • Addition of EDA DFT tools • Addition of test & burn-in sockets and test interface boards • Increased focus on RF

3. 2005 ITRS Test Chapter Revision • Trends described in 2001 have held true • High speed serial I/O appeared across market segments • SOC and SIP occurred in significant numbers • Low cost, flexible (open arch) targeted test, platforms emerging • Increasing integration of analog/RF • 2003 Test Chapter focused on key challenges • Less emphasis on evolutionary trending • Increased effort to identify, define, & discuss the key test challenges • 2005 Test Chapter • Continue to focus on concise key challenges • Consolidating Logic (formerly separate ASICs, CPUs) • Addition of test sockets, DFT EDA

4. Key Test Drivers • Device Trends • Device interface bandwidth (data rate & pin count) • Increasing device functionality & integration (SOC, MCP, SIP) • Package form factor & electrical / mechanical characteristics • Device architectures that could break the stored stimulus & response test model (e.g. power management, redundancy) • Emerging Technologies • RF, Analog, Optical, MEMs • Increasing Test Process Complexity • To enable device customization, optimize test flow • To provide better and faster manufacturing feedback • Bottom Line Constraint is Test Cost • Boundary conditions: Affordability and maximum allowable DPM

5. Key Test Challenges & Opportunities • Enabling cost effective testing of: • High speed device interfaces • Highly integrated designs, SOCs, MCPs, & SIPs • RF and other emerging technologies • Testing for reliability • Containing and optimizing total product test cost • Detecting and isolating new defects and failure modes • Improving test efficiency • Automation and standardization of generating test content. • Developing the infrastructure to handle and more effectively use increasing test data volume to enable product customization, drive yield learning and provide process feedback • Correlating the test environment (& results) to end use.

6. Potential Test Solution Space • Includes test equipment, test tooling (e.g. probe cards), DFT and test factory infrastructure. • The optimum combination is product dependent and is driven by cost and test goals.

7. Backup

8. High Speed Serial Interfaces • Penetration of high speed interfaces into new designs continues to increase • Leading edge communications devices data rate trend extends further into GB/s • High speed serial links (1.5 to 4 Gbps, 10s to 100s) becoming ubiquitous across product types / business segments / formerly plain vanilla digital products • Transaction / event driven protocols inconsistent with stored response ATE / mfg test • Simple Loopback alone may not be sufficient to achieve needed product quality • I/O Test and DFT methods must be continue to expand deployment as well as advance more new features to enable cost effective production test and product quality

9. Analog and RF • Analog and RF circuits are pervasive in digital world • Mobile/wireless as % of semis increasing • Circuit performance envelope increasing • Test method innovation required • Primary test solutions continue to be based on expensive functional and parametric methods • Relatively little DFT has been developed, and what does exist lacks industry momentum • Test TWG needs increased participation in the analog/RF trends and requirements development

10. SOC, MCP, and SIP • Customer requirements for form factor and power consumption are driving a significant increase in design integration levels • Test complexity will increase dramatically with the combination of different classes of circuits on single die or within a single package • Disciplined, structured DFT is a requirement to reduce test complexity • Increased focus on KGD and sub-assembly test driven by cost for SIP • Mems, opticals, and other emerging or newly integrated to SIP and silicon systems and devices • SIP/MCP physical FA is much more difficult, • Test diagnostics will be more critical moving forward

11. BISR/BIRA Path Delay Test Strategy Analog Isolation BOST Scan+ATPG IP Core Isolation BIST Analog DSP Control Memory Logic MCU IP Core Based Design Test Implications of IP Design • Test Strategy and Integration • DFT for IP Core Based Design • Higher Level DFT • Standardization

12. IP Core Test Wrapper Insertion SoC Test Wrapper DFT DFT Test Data Test Data Conversion Test Controller Chip-Level Test Data Configuration of Chip-Level Test Controller and Test Access Mechanism Automated DFT Insertion • Automation of test control integration and test scheduling • Insert test wrapper and test control circuits

13. Reliability Screens Run Out of Gas • Critical need for development of new techniques for acceleration of latent defects • Burn-in methods limited by thermal runaway • Lowered use voltages limits voltage stress opportunity • Difficulty of determining Iddq signal versus “normal” leakage current noise • New materials and devices • Rate of introduction increasing: Cu, low k, high k, SiGe • Critical interactions of new materials increasing (Cu / low k), leadless pkg • More integration of silicon systems (MEMs, optical) appearing • More device permutations even in vanilla CMOS • Increasing mechanical and thermal sensitivities

14. The Overall Cost of Test $ NRE Costs $ DFT design and validation $ Test development $ Device Costs $ Die area increase $ Yield loss $ Work-Cell Cost $ Building Capital $ People $ Consumables $ Loadboards, DUT interface $ Capital Equipment Depreciation of: $ Test Equipment $ Handler/Prober Work-Cell Good Units Shipped Untested Units • Goal is to optimize product cost • Must strike a balance between cost/value of design, manufacture, yield learning, and test UPH/$M Effectiveness Measure Rejected Units

15. Test Capability Treadmill • DFT and test methods development is effectively constraining logic test requirements • Capability driven investment into equipment for testing Analog, RF, and SerDes circuits • MCP, SiP, and SoC drive convergence of leading edge, high density logic with flash, DRAM, SRAM, analog, RF, and SerDes • The move toward open architecture is intended to make it easier (and cheaper) to implement incremental capability while enabling reuse

16. Failure Analysis and Diagnosis • Enhanced automated software diagnostic capabilities to improve physical failure analysis ROI • Characterization capabilities must identify, locate, and distinguish individual defect types • Increased accuracy and throughput (days to hours) • Failure analysis methods for analog devices must be developed • DFT is essential to localize failures • Improve efficiency and reduce design complexities associated with test • Defect types and behavior will continue to evolve with advances in fabrication process technology • Fundamental research in existing and novel fault models to address emerging defects will be required

17. Automated Test Program Generation • Tools for ATE software and test program generation are needed to decrease test development effort and improve time to market • Automated design to manufacturing test program flow • Correct by construction (pre-silicon) • Interoperability standards (STIL, CTL, etc) • Enable test content portability among test platforms • ATE S/W operating environment standards • Direct impact on time to market and product development cost • Driven by product complexity and shorter product cycles