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Silicon Detector Tracking

Silicon Detector Tracking. ALCPG Workshop Cornell July 15, 2003 John Jaros. SD Tracking Philosophy. Si/W calorimetry is expensive, so limit $ by limiting radius and length of tracker

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Silicon Detector Tracking

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  1. Silicon Detector Tracking • ALCPG Workshop Cornell July 15, 2003 John Jaros

  2. SD Tracking Philosophy • Si/W calorimetry is expensive, so limit $ by limiting radius and length of tracker • Get back BR2 by raising B (~5T) • Maintain tracking resolution by using Si strips • Pillbox tracker shortens z, minimizes material for forward tracking, calorimetry, e ID • 5 layer VXD ensures good pattern recognition • 5 layer barrel measures momentum, confirms trajectory for particle flow calorimetry

  3. SD Tracking Concept Layout Performance • Solid Angle coverage to ~100 mr • p/p2= 2 x 10-5 • 5 Layers of CCD + 5 Layers Si strip

  4. SD Barrel Tracker Concept • Si Ladders. Build on GLAST development. Daisy-chain detectors to barrel half-lengths. • Axial or Small Angle Stereo • Readout. Bump bonded ASIC: Preamp, shape, discrimminate, compress, transmit. Pulsed power. • Support. Low mass C-fiber space frame.

  5. Some SD Tracking Issues • How robust is pattern recognition in the presence of backgrounds? SLD experience + Tesla studies lend credance to VXD pattern recognition capability.Full simulation studies are underway for VXD and Barrel given VXD. • Can K0 s and  s be tracked? Does it matter for P-Flow Calorimetry?Needs study. • How are exotic, heavy, long-lived particles (which decay outside the VXD) tracked?Needs study. • Do mini-jet () backgrounds need good time resolution?Under study.

  6. Is SD Pattern Recognition Robust?Two Approaches • Plausibiltiy Argument (see below)1. Presume VXD pat rec is fully efficient2. Assume VXD tracks can be extrapolated to barrel if barrel occupancy is low enough. Need a realistic estimate of occupancies • Full Geant4 Simulation, including1. All machine related backgrounds2. Interactions of backgrounds in detectors3. Realistic detector response and noiseGenerate and process “raw” dataPattern recognize from “measured” hits

  7. Barrel Occupancy @ NLC Backgrounds T. Maruyama High pT pairs from Hit density from pairs beamstrahlung~MeV photons frompairs showering nearquad faces Photon Z Distribution (cm) @ R=25cm Photon Energies (MeV) @R=25cm 0.1 1 10

  8. 300 m Si layer in a uniform magnetic field. The layer is divided into 50 m wide strips. Energy deposition is calculated in each strip. Ecut = 10 keV E:: <.1, .1-.5, .5-1, >1 MeV , Converted Electrons can exit Si B = 5 Tesla EGS SimulationT. Maruyama

  9. Tracker Layer 1 Simulation • Photon flux: 241 photons/4 bunches • 5784 photons/NLC train • Detector response: 113 keV/MinI 30 keV threshold • 25k Channels/Half Barrel No. of hits: 68 strips/train 69 strips/train 106 strips/train Occupancy: 0.27% 0.28% 0.42%

  10. Barrel Occupancy/Train • Summary for Layer 1 (half barrel r=25cm) Photon Hits 0.42% e+e- Hits ~0.10 % Noise Hits 0.20% Total Occupancy 0.7 % • Effect on Tracking Estimate probability that hits from a track of interest are compromised. Require no background hits in 2 strips track hits or the 2 adjacent strips. P=(1 - .007)4 = 97.2 % • SD Pattern Recognition looks OK

  11. SD Forward Tracking Ideas • Extend barrel tracking philosophy forward 1. Pattern Recognize in 5 Layers of CCD 2. Extrapolate tracks to forward disks for momentum measurement and reliable extrapolation to the calorimetry. 3. Global Pattern Recognition to follow • Design Considerations 1. Extend 5 layer tracking over max  2. Minimize CCD area/cost 3. Thin the CCD barrel endplate

  12. SD Inner Tracker Concept •  Coverage 5 CCD layers .97 (vs .90 TDR VXD) 4 CCD layers .98 (vs .93 TDR VXD) • Shorten Barrel CCDs to 12.5 cm. Thin endplate. • Multiple CCDs on a single 300 m Si disk?

  13. SD Inner Tracker PerformanceCourtesy B. Schumm and LCDTRK R-Z Impact Parameter Resolution (m)New SD Old SD -log10(1-cos)90 60 41.5 29 20.5 14.5 10.2 degrees

  14. SD Tracking - Design Exercise • Goal: Bring SD Tracking Design to CDR stage Realistic, pre-engineering design study • In particular 1. Define SD Tracking Concepts 2. Demonstrate Concept Works (or fix it!) e.g. pattern recognition with backgrounds 3. Develop the Physical Picture (ladders, supports, readout and power connections, cooling, alignment,…) 4. Detector and Readout R&D • Who?U Oregon, UCSC, SLAC… • Help Needed

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