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ATLAS Local Trigger Processor

ATLAS Local Trigger Processor. P. Borrego Amaral a , N. Ellis a , P. Farthouat a , P. Gallno a , H. Pessoa Lima Junior b , T. Maeno a , I. Resurreccion Arcas a , J. M. de Seixas a , G. Schuler a , R. Spiwoks a , R. Torga Teixeira a , T. Wengler a a CERN b University Rio de Janeiro.

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ATLAS Local Trigger Processor

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  1. ATLAS Local Trigger Processor P. Borrego Amarala, N. Ellisa, P. Farthouata, P. Gallnoa, H. Pessoa Lima Juniorb, T. Maenoa, I. Resurreccion Arcasa, J. M. de Seixasa, G. Schulera, R. Spiwoksa, R. Torga Teixeiraa, T. Wenglera a CERN b University Rio de Janeiro

  2. Level-1 Trigger Overview ATLAS Local Trigger Processor

  3. Why a Local Trigger Processor module? • Need for an interface between the Central Trigger Processor and the TTC partitions • TTC signals transmission • Dead-time (BUSY) handling • Calibration requests capability • Need for stand-alone operation of partitions • Including capability for running several partitions • Dealing with dead-time • LTP module and CTP-Link ATLAS Local Trigger Processor

  4. TTC Partition Root • 4 modules • LTP • TTCvi • TTCxx (vx, ex or tx) • ROD-BUSY module • LTP receives the CTP-Link from the CTP and allows to run in stand alone mode • i.e without the CTP ATLAS Local Trigger Processor

  5. CTP Link • It contains  • One link per sub-detector • Several LTPs daisy chained on this link • Up to 20 links delivered by the CTP • LVDS signals ATLAS Local Trigger Processor

  6. LTP Basics • Contains the interface to CTP functionality • Connection to the CTP with possibility to daisy chain • Output link • Connection to the TTCvi and TTCxx (TTCex or mx or vx) • Contains all the tools to generate local triggers, local commands (B-Go), trigger-type • Handles the dead-time when in local mode • Is able to act as a master on the output link • Allows to easily drive several TTC partitions from one LTP • Assuming they are on the same link • Mainly for TTC partitions from the same sub-detectors ATLAS Local Trigger Processor

  7. LTP in global mode • Get all the timing and trigger signals from the CTP • BC, Orbit, ECR, Pre-Pulse, L1A • Send the Busy signal and the calibration requests to the CTP ATLAS Local Trigger Processor

  8. Calibration requests • Input to CTP: • Each sub-detector: 3-bit calibration trigger • 16 sub-detectors and other sources of calibration triggers defined • CTP contains 4-bit LHC turn counter: each turn is assigned to one sub-detector • Generate L1A when: • Calibration trigger input has value ≡ 1 .. 7 • Current LHC turn is allocated to the sub-detector • Current BCID is in BCID group for calibration: e.g. empty bunches, large gap • No dead-time generated by CTP, no external BUSY • Identify calibration trigger: • Trigger type word • Timing to be set-up by sub-system • e.g when should a pulser fire to get data in phase with L1A ATLAS Local Trigger Processor

  9. Role of the LTP in Stand-alone Mode • Generates local trigger and handles locally the dead-time • Generates “Trigger_type”, synchronisation signals, … for some special calibration runs • Must allow to have several separate partitions from several sub-detectors running together • e.g Calorimeter(s) with Level-1 calorimeter ATLAS Local Trigger Processor

  10. LTP in stand-alone mode • Use local triggers and local commands • May still use BC and Orbit from the CTP • Handle the Busy to introduce local deadtime • May drive its output CTP Link towards other LTPs and receive Busy signals from these other LTPs ATLAS Local Trigger Processor

  11. CTP link output CTP link input Programmable Switch + Pattern Generator + Logic Local outputs BC, L1A, Local Triggers Commands, Busy, BGo<i> Local inputs BC, Local Triggers, Local Commands, Busy, Calibration Req. Block Diagram ATLAS Local Trigger Processor

  12. Internal Pattern Generator • An internal sequencer allows to generate any signal at any given time within a LHC turn • Can be used in global mode to send to the CTP the 3-bit calibration request • Can be used in stand-alone mode for generating any signal • Triggers, BGo<i>, … • 1 MWord RAM • Read-out with BC  26 ms time coverage • One shot or continuous mode • Can be started by ORBIT or Pre-Pulse or a VME access ATLAS Local Trigger Processor

  13. Global modeor Slave in Local mode • STATUS • (VME) CTP- LINK (LVDS) CTP- LINK (LVDS) LVDS PECL PECL LVDS CTL (VME) Internal Busy Signal (TTL) Master in Local mode CTL (VME) Mask from Pattern-Generator CTL (VME) PECL ECL L1A<0> to TTCvi (ECL/dc) Mask from Inhibit-Timer CTL (VME) CTL (VME) Dead-Time Generation ECL NIM L1A<0> to Local Logic (NIM) Local mode Or Master in Local mode CTL (VME) BC NIM TTL External L1A trigger (NIM) PFN ( 1 or 2 ) * BC From Pattern- Generator ‘0’ CTL (VME) TTL PECL TTL PECL L1A Path ATLAS Local Trigger Processor

  14. STATUS (VME) 3 CTP - LVDS 3 TTL CTP - LINK LINK TTL LVDS (LVDS) (LVDS) CTL (VME) TTL 3 Test Triggers To TTCvi Internal (NIM) Busy NIM Signal 3 (TTL) CTL D Q (VME) TTL 3 Mask from Test Triggers Pattern - To Local Logic Generator (NIM) NIM BC CTL CTL (VME) (VME) Mask from Inhibit - Timer CTL Dead - Time (VME) Generation CTL (VME) BC 3 NIM External PFN Test triggers ( 1 or 2 ) * BC (NIM) TTL ‘0’ From Pattern - Generator CTL (VME) Test Triggers path ATLAS Local Trigger Processor

  15. Transparent STATUS STATUS (VME) (VME) CTP - CTP - LVDS TTL LINK LINK From Pattern - TTL LVDS Generator (LVDS) (LVDS) CTL STATUS (VME) (VME) Busy From To internal BUSY - trigger MODULE blocking logic TTL STATUS CTL Busy In BC from local (VME) (VME) logic NIM (NIM) CTL Global mode (VME) STATUS (VME) TTL Bu sy Out to local Mask from logic or NIM Pattern - Monitoring Generator (NIM) Mask from CTL Inhibit - (VME) Timer CTL (VME) L1A TestTrig1 Dead - Time up to 8*BC TestTrig2 TestTrig3 BC VME CTL (VME) BUSY path ATLAS Local Trigger Processor

  16. Pattern Generator Block Diagram SRAM ADDR Counter SRAM 1 Mword x 16-bit 12 ns BC Clock Pattern SRAM Data Port SRAM RD / WR / RUN SEQUENCER STATE MACHINE ADDR CNT Shadow reg. CS*WR*SRAM CS*WR*ACR CSR CS*RD*<addr> Read VME Data MODE (CSR) CS*WR*CSR Output Pipeline Register RD Pipe- Line Reg. Predefined Values Pattern Generator Output VME Data Bus BC Clock Fixed Value Reg CS*WR*<addr”> ATLAS Local Trigger Processor

  17. Orbit path Global mode or Slave in Local mode LVDS PECL CTP- LINK IN (LVDS) PECL LVDS CTP- LINK OUT (LVDS) Master in Local mode CTL (VME) STATUS (VME) PECL ECL ORBIT to TTCvi ECL/dc TTL PECL CTL (VME) PECL NIM ORBIT or TURN to Local Logic (NIM) TTL PECL CTL (VME) PECL TTL CTL (VME) ‘0’ TTL NIM ORBIT 4 bit Counter/ “TURN” generator Divide by 3564 RST by ECR Start Timer Trigger/BGo Inhibit 12 bit Timer and Shadow register Trigger/BGo Inhibit (4*BC wide) System Clock (BC) BC External Orbit (NIM) TURN number from VME From Pattern- Generator/ Sequencer Local mode or Master in Local mode Inhibit window position from VME ATLAS Local Trigger Processor

  18. Trigger Type path Global mode or Slave in Local mode CTP- LINK IN (LVDS) LVDS TTL 8 TTL LVDS CTP- LINK OUT (LVDS) CTL (VME) VME TTL ECL TRIG-TYPE/ecl (to TTCvi) 8 DQ Register File 4 bytes deep CTL (VME) CTL (VME) Test Path BC 2 ECL TTL Local mode or Master in Local mode From Pattern- Generator/ Sequencer Counter Reset by VME function FIFO L1+Trig[3:1] ORBIT Bgo[3:0] ‘0’ 32 bit counter VME CTL (VME) VME ATLAS Local Trigger Processor

  19. Technology • LVDS on the CTP LINK • Internal logic in PECL for BC, ORBIT and L1A • 5V TTL remaining logic • NIM and ECL for external connections to the TTCvi and local equipment • CPLD’s by ALTERA (ISP) Cable & Connectors • CTP LINK Cable: 25 twisted pairs screened, max length 30 m • Cable skew tests has been done – will wait for test-beam results – before deciding on final selection of cable brand • See EDMS document: ATL-DA-TN-0001 • Local (short) cables, linking LTP’s together, can be flat cables • 50 pin 3M Micro Delta Ribbon connectors are used ATLAS Local Trigger Processor

  20. Logic implementation Firmware in 8 CPLD’s • Pattern Generator Control and FSM • Pattern Generator Memory Address Counter • BC & ORBIT paths’ CSR’s, BC divider, Inhibit Timer, Event Counter • Trigger Selector MUX and CSR’s for L1A and Test Triggers • Trig-Type Register File, CSR, Diagnostic FIFO ctl • B-Go[3..0] source selector and associated CSR’s • BUSY and Dead-Time logic & selector, CSR, Calibration path, TURN counter • VMEbus Interface and Interrupter ATLAS Local Trigger Processor

  21. Status • 6 LTP modules assembled • Tested and debugged • All functions works • In system tests during October 2004 25 ns test-beam run • Documentation in progress and partly entered in the EDMS • EDMS Description: Atlas_LTP / EDMS Id: EDA-00508 v.0 ATLAS Local Trigger Processor

  22. LTP Pictures ATLAS Local Trigger Processor

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