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John O. Borland, J.O.B. Technologies, Aiea, HI Yoji Kawasaki, Renesas Technology, Itami, Japan

32nm Node USJ Formation Using Rapid Process Optimization Metrology & Updates From March MRS, May IWJT, May ECS, June IIT and June VLSI Sym. John O. Borland, J.O.B. Technologies, Aiea, HI Yoji Kawasaki, Renesas Technology, Itami, Japan Brian Chung, KLA-Tencor, San Jose, CA

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John O. Borland, J.O.B. Technologies, Aiea, HI Yoji Kawasaki, Renesas Technology, Itami, Japan

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  1. 32nm Node USJ Formation Using Rapid Process Optimization Metrology&Updates From March MRS, May IWJT, May ECS, June IIT and June VLSI Sym John O. Borland, J.O.B. Technologies, Aiea, HI Yoji Kawasaki, Renesas Technology, Itami, Japan Brian Chung, KLA-Tencor, San Jose, CA Jeffri Halim, Frontier Semiconductor, San Jose, CA Solid State Technology July 2008

  2. Outline • Introduction • <10nm Ultra-Shallow Junction • Junction “Quality” (Rs dopant activation, junction leakage and residual implant damage after annealing) • Micro-uniformity variation • USJ Implantation • USJ Annealing • Process Integration Issues • FinFET Doping • Summary

  3. Design For Manufacturing: Controlling Process Variability Key For sub-45nm Node Manufacturing! Delta Vt=>100mV (0.1V)! -Process proximity effects -Layout loading effects -Gate line edge roughness effects -Implant dopant positioning -Thermally induced variation by RTA (& msec anneal) Key will be Characterization, Reduction & Accommodation T.C. Chen, IBM, IEEE Solid State Circuits Society Newsletter, Vol. 20, No. 3, Sept 2006, p.5

  4. 3 Main Sources Areas Of Device Leakage • Gate Leakage • High-k/Metal Gate reduce gate leakage by >1,000x • Source Drain Leakage • Engineer the location of EOR damage to reduce junction leakage • Gate Edge Leakage • Extension/HALO junction leakage influenced by band to band tunneling, HALO dose, extension abruptness and shallow EOR damage Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04

  5. C.-H. Jan et al., IEDM 2005, p.65 Advanced USJ Requirements • Minimize Dopant Diffusion • Maximize electrical activation • “Enough” defect annealing • Junction leakage: Small part of total power, but significant for low power CMOS • High channel/halo doping greatly increases leakage • Need to optimize all 3 “dimensions” • Damage metrology: • Traditional - TEM, devices • Non-Contact: • RsL – RS & Junction Leakage • Thermal-wave Slow and costly! Rapid Process Optimization P. Timans et al., MRS 2008

  6. 25 (IBM) 32nm Node Xj= 8-20nm so B (150eV-600eV)! MRS March 2008 NO due to MSA micro-uniformity & unstable defects needs post diffusion-less spike/RTA! J.O.B. Technologies (Strategic Marketing, Sales & Technology) 6

  7. (A/cm2) E-0 E-1 E-2 E-3 E-4 E-5 IMEC, VLSI Sym 2008, paper 19.1

  8. E-2 E-4 E-6 Borland, IWJT 2008

  9. RsL Leakage Range HALO Dose Effects On RsL & Diode Leakage SPE:Si-PAI SPE:Ge-PAI SPE:Ge-PAI Flash:Ge-PAI RsL Flash:RsL Spike:RsL Spike 9 Borland, IWJT 2008

  10. Outline • Introduction • USJ Implantation • Single wafer implanter design • Elemental species (energy, dose) • USJ Annealing • Process Integration Issues • FinFET Doping • Summary

  11. Kuroi & Kawasaki, USJ 2005

  12. Greatest TW Change Is In Diagonal Scan!

  13. JOB/IMEC USJ Study B 500eV TW=667 20keV Ge-PAI+B TW=2900 5keV Ge-PAI+B TW=1520 DSA 1210C TW=24 Stable Defects Rs=579 DSA 1210C TW=140 Unstable defects Rs=521 DSA+Levitor 900C Spike TW=19 Stable Defects Rs=627 DSA+Levitor 900 Spike TW=130 Unstable Defects Rs=616

  14. MRS March 2008

  15. Selete Demonstration of SDE Tilt ~15% J.O.B. Technology (Strategic Marketing, Sales & Technology) 15 Ootsuka et al., IEEE Trans Electron Devices, April 2008, p.1042

  16. 7% Improvement Due To Gate Overlap Control Fujitsu, VLSI Sym 2008, paper 19.2

  17. Lateral Graded Single-S/D Use Selective Poly To Eliminate Facet Issues A1 B1 B4 A4 A2 Sel. Epi Sel. Epi B3 B2 1x dose 3x dose 5x dose SOI 7x dose 8x dose (A&B) Terraced penta SS/D formed by 0 & 45 degree twist octa (8)-mode implant A3 (A) Terraced triple SS/D formed by 0 degree twist quad-mode implant Sel. Poly Sel. Poly Sel. Poly Sel. Poly 2x dose 4x dose 4x dose 3x dose 1x dose SOI SOI 1&3, 2&4 Borland, Moroz, Wang, Maszara & Iwai, Solid State Technology, June 2003 (B) Terraced double SS/D formed by 45 degree twist quad-mode implant

  18. Gate OverLap Control: Tilt nSDE & PAI (0o-vs-30o) Box Shape Rp=3.7nm Xj=14.7nm Yj=0-3.3nm Yj/Xj=0-0.22 Rp=3.3nm Xj=15.3nm Yj=8.3nm Yj/Xj=0.54 Sin20o=0.34x Sin30o=0.5x Sin45o=0.71x J.O.B. Technology (Strategic Marketing, Sales & Technology) 18 Borland & Moroz, Semiconductor International, p.72, Apr. 03

  19. Future: Phosphorus Replacing Arsenic?(1keV/1E15/cm2, 0 & 30 Degree Tilt) 0o Tilt 30o Quad Tilt Ge-PAI & 30o Quad Tilt Xj=12nm Yj=3-5nm Yj/Xj=0.42 Xj=13nm Yj=7nm Yj/Xj=0.53 Xj=9nm Yj=7nm Yj/Xj=0.78 Box Shape V. Moroz, Synopsys (Mar. 03)

  20. Annealing Companies • US • Mattson fRTP • Applied laser DSA • UltraTech laser LSA • Japan • DNS Flash lamp (FLA) • Metrology For Rapid Process Optimization • KT • Thermal-Probe (TW) for implant damage and after anneal damage recovery (residual implant damage) • Frontier • RsL sheet resistance and junction leakage current • Equipment Companies • US • Varian (VIISta-HCS & -PLAD) • Carborane option • Axcelis (Optima-HD) • Imax (molecular dopant) • AIBT (i-Pulsar) • EC filter so >10/1 decel ratio with no energy contamination • SemEquip (molecular dopant) • B18, C7, C14, P4, etc. • TEL-Epion (infusion doping) • B2H6, GeH4 • Japan • SEN/Axcelis (SHX) • 40/1 decel! • Nissin & SemEquip

  21. Outline • Introduction • USJ Implantation • USJ Annealing • Diffusion-less dopant activation and implant damage recovery • Spike+msec, msec+spike or msec+spike+msec annealing sequences • Process Integration Issues • FinFET Doping • Summary

  22. DSA Laser Stitching Pattern Effect On Device Variation! IMEC, VLS I Sym 2008, paper 19.1

  23. 25mm 300mm 3.6mm 50mm 3.6mm JOB/IMEC DSA USJ Analysis 3.6mm

  24. DSA: 5keV Ge-PAI+B DSA+Spike: 5keV Ge-PAI+B

  25. fRTP RsL & TW Wafer Map & Line Scan Rs=1.5% TW=3.6%

  26. RsL & TW Map & Line Scan of Sweeping Laser Rs=2456 (1.8%) Peak to peak Rs=+/-7.5%

  27. Rs=8.5% global and 1.5% local

  28. TW=26%, Rs=8.5% Rs=2.8% J.O.B. Technology (Strategic Marketing, Sales & Technology) 28

  29. NEC & Selete IWJT 2007:Differences For Flash & Spike Results Temperature? Bss (atoms/cm3) J.O.B. Technology (Strategic Marketing, Sales & Technology) 29 Borland’s IWJT 2007 Joint NEC (S4-8) and Joint Selete (S4-7) papers

  30. PAI Enhanced Activation At Lower Flash Temperatures But EOR Damage/Leakage 1175C! J. Gelpy Kato et al., Selete, IWJT 2007, p.143 J.O.B. Technology (Strategic Marketing, Sales & Technology) 30

  31. DSA Laser Requires Deep Ge-PAI So USJ Will Be Leaky! IMEC agrees DSA -75C! March 2008 T. Noda et al., SSDM 2007, paper A-5-1, p. 712 1225C!

  32. RsL Sheet Resistance (ohms/sq.) <1150C? >1325C? Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology July 2008

  33. 1.2E20/cm3 1.2E20/cm3 Nara et al., Selete, ECS May 2008

  34. LSA power level 6 LSA power level 5 LSA power level 4 LSA power level 3 LSA powerr level 2 LSA power level 1 Borland et al., JOB/Renesas/FSM/KT, Solid State Technology, July 2008 34

  35. RsL Junction Leakage Current (A/cm2) Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008

  36. Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008

  37. <1150C----------------------------------------->1350C B 5keVGe+B 20keVGe+B

  38. Thermal-wave Units Stable Defects No anneal <1150C <1250C >1325C <650C Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008

  39. No Ge-PAI Residual EOR Damage At <7nm Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04 Mineji et al., Selete, SSDM 2004, Sept. 04

  40. Lower Energy Ge-PAI & Higher MSA Peak Temp or Post 950C Spike RTA Reduces EOR Defects Density! 700oC iRTP, 1100oC fRTP + 950oC Spike RTA 700oC iRTP, 1200oC fRTP 700oC iRTP, 1100oC fRTP 700oC iRTP, 1300oC fRTP 66nm 66nm 66nm 66nm R. Camillo-Castillo et al., U of F, MRS Spring meeting 2008, paper E6.9

  41. J.O.B. Technologies (Strategic Marketing, Sales & Technology) J.O.B. Technology (Strategic Marketing, Sales & Technology) 41 41 V. Moroz et al., MRS Spring meeting, paper E6.6

  42. Yeong et al., CSM, IIT-2008

  43. 900C Spike 1st+FLA For Low Leakage & Complete Damage Annealing With 10keV Ge-PAI RsL Sheet Resistance (ohms/sq.) Borland et al., JOB Tech/Selete/Nanometrics, IWJT 2007 RsL Junction Leakage Current (A/cm2) J.O.B. Technologies (Strategic Marketing, Sales & Technology) 43

  44. Extension Results (Leakage) RsL Junction Leakage Current (A/cm2) Yamamoto et al., IWJT 2008, MSA pins F in substitutional site and degrades leakage! F effect: Noda (MRS 2008), Yamamoto (IWJT 2008), England (IIT 2008 P41) J.O.B. Technologies (Strategic Marketing, Sales & Technology) 44 >1200C?

  45. Thermal-wave (TW units) Extension Results (TW) PAI-EOR Damage Stable Defects Borland & Kiyama, JOB/DNS, IIT-2008

  46. TW >100 Reveals Residual Implant Damage After Diffusion-less Flash & SPE Anneals SPE Ge+B B Ge+BF2 Flash SPE+Flash Spike Spike+Flash Flash+Spike Flash+SPE Good leakage with EOR damage Stable Defects Unstable Defects Borland & Kiyama, JOB/DNS, IIT-2008

  47. Rs Sheet Resistance (ohms/square) HALO Results (Rs) In dopant activation limited by solid solubility B dopant activation limited by dose

  48. P-Halo (In, B10, BF2) Leakage current density In case of indium I/I, a leakage current was detected by RsL. The leakage current depend on the anneal condition. ⇒ High temperature annealing can reduce the leakage. 48 Mienji, Borland et al., NEC/JOB/Nissin, IWJT 2007

  49. RsL Leakage Correlation To Diode Leakage Hatem et al., VSEA, IIT-2008

  50. Leaky! Good! C. Hatem, VSEA IIT 2008 RsL (PR1-vs-Ge-PAI+C) RsL LSA-1 power RsL SPE RsL LSA-6 power <1150C <650C >1350C 20keV Ge-PAI 10keV Ge-PAI 5keV Ge-PAI No PAI Borland, Matsuda & Sakamoto, joint NEC paper, Solid State Technology, June 2002, Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008 & Kawasaki et al., IIT 2008 J.O.B. Technologies (Strategic Marketing, Sales & Technology) J.O.B. Technologies (Strategic Marketing, Sales & Technology) 50 50

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