Device Interface Board for Wireless LAN Testing

1. Device Interface Board for Wireless LAN Testing Team May 06-15 Client ECpE Department Faculty Advisor Dr. Weber Team Members Matthew Dahms – EE Justine Skibbe – EE Joseph Chongo – EE Srisarath Patneedi – CprE December 06, 2005

2. Presentation Outline • Project Activities • Technology Considerations • Present Accomplishments • Hardware • Software • Planned Activities • Design • Closure Materials • Schedule • Closing Summary • Project Overview • Introduction • Problem Statement • Assumptions and Limitations • System Considerations • User Considerations • End-Product Description • Overview of Existing Work • May 05-29 Team’s Accomplishments • Parallel-Serial Conversion • Transmitters and Receivers • FPGA

3. 1 0 1 0 D3 D2 D1 D0 voltage time Header Data Packet Definitions • ASK modulation – Amplitude shift keying. In this modulation scheme the amplitude is varied to indicate logic 0’s and 1’s • DUT – Device under test (positive edge D flip-flop) • Header – Preamble bits sent prior to the sending of information in a data packet Data Packet and Header

4. Definitions (cont.) • NRZ – Non-return to zero. Using NRZ, a logic 1 bit is sent as a high value and a logic 0 bit is sent as a low value. • PLL – Phase-locked loop • RZ – Return to zero. This is the opposite of NRZ data. The signal state is determined by the voltage during the first half of each data binary digit.  The signal returns to a resting state (called zero) during the second half of each bit.

5. Project Overview

6. Acknowledgement • Dr. Weber • Nathaniel Gibbs (GibbaHertz) • Jason Boyd

7. Introduction • Teradyne Integra J750 • Digital Tester • Donated to Iowa State • Desire to test wireless chips using J750 • May 05 project was first step toward that goal • Created send/receive network to test digital device remotely • Programmed FPGA for simple tests Teradyne Integra J750

8. Project Overview • Problem Statement • S/R network exists but no method is available for clock recovery • Must develop a clock recovering circuit and integrate it with current system • Investigate realistic range of operation for the wireless interface

9. Project Overview • System Constraints • The Teradyne J750 must operate within +/- 3° C of calibrated temperature (30° C). • The maximum rate at which data may be sent is at 115.2 Kbps. • The Tx and Rx networks communicate at 916.5 & 916MHz. Nearby wireless signals at similar frequencies may disrupt the setup. • The IG-XL software shall be used in writing the test data sets for the Teradyne J750. • Only one FPGA will be provided.

10. Project Overview • Users Assumptions • The user has knowledge in electrical and/or computer engineering. • The user has previous experience testing circuits with the Teradyne J750. • The user has read the Teradyne J750 instruction manual and will observe all necessary safety precautions as prescribed in that manual. • Intended Uses • Functional test of a digital device • (Future) Wireless chipset test

11. Project Overview • End-Product and Other Deliverables • Wireless interface with clock recovery circuit • Demonstration of wireless test • Update the manual for wireless test operation Cover page of wireless manual

12. Overview of Existing Work

13. Overview of Existing Work • May 05-29 Accomplishments • Parallel-Serial Conversion • Transmitters and Receivers • Processing Device

14. Overview of Existing Work • Parallel-Serial Conversion • Needed to convert parallel test data into serial test data • Chose to use a shift register Shift Register attached to daughterboard

15. Overview of Existing Work • Transmitters and Receivers TRM1 RCV1 RCV2 TRM2

16. Overview of Existing Work • FPGA • Used to recognize header signal • Identifies test data • Presents test data to DUT • Presents reply to S/R network

17. Final System Setup

18. Project Activities

19. Project Activities • Project Definition • Part of the May 05 team’s project definition was to include a clock recovery circuit, but due to timing constraints was unable to do so. • May 06 goal is to integrate a PLL for clock recovery with the existing network.

20. Project Activities Design

21. Project Activities • Technology Considerations • Manchester vs. PLL • NRZ to RZ Conversion • Software

22. Project Activities Manchester Encoding The waveform for a Manchester encoded bit stream carrying the sequence of bits 110100

23. Project Activities • Manchester Encoding • Very easy to implement • Clock phase and frequency are both present • Too fast for current transmitters and receivers!

24. Project Activities • Phase Locked Loop • Must be “trained” • Test data must follow a training signal • More difficult to implement • Don’t have to build new transmitters and receivers

25. Project Activities • Present Accomplishments • Hardware • Previous team’s project setup and tested • PLL • Monostable Multivibrators • Software • Prototype control software for FPGA written • IG-XL test template written

26. Project Activities Internal Components of a PLL

27. Project Activities • Phase Detector • Type I – XOR • *Type II – Generates lead or lag pulses • Voltage Controlled Oscillator (VCO) • Centered at 115.2 KHz • Frequencies too far off of center frequency will not lock

28. Project Activities

29. Project Activities • Monostable Multivibrators • Chosen to convert NRZ data to RZ data • Must use an external RC combination to specify pulse widths

30. Project Activities NRZ to RZ converter circuit with I/O waveforms

31. Project Activities • Software • FPGA serves as “brains” of system • Verilog chosen to program FPGA • Prototype code complete

32. Project Activities

37. Project Activities • Planned Design/Test Activities • Build and Test NRZ to RZ Converter • Build and Test PLL Circuitry • Integrate Clock Recovering Circuitry • Modify FPGA Code as Necessary • Test Functional Range of Wireless Interface

38. NRZ/RZ PLL

39. Closure Materials

40. Closure Materials • Expected • Actual • Updated Schedule

41. Closure Materials Schedule (cont.) • Expected • Actual • Updated

42. Closing Materials • Lessons Learned • What technical knowledge was gained? • FPGA implementation • Teradyne Integra J750 usage • Clock recovery methods • System integration

43. Closing Materials • Lessons Learned • What went well? • May05 System still works! • Teamwork • Learned to work in arctic environments (19 degrees C inside Teradyne lab) • What did not go well? • Locating May05 equipment • Initial Teradyne J750 setup and test • Uploading program to FPGA • FPGA inputs pins

44. Closing Materials • Closing Summary • Problem – Integrate clock recovery circuitry into current system • Solution • Use PLL for clock recovery • Modify FPGA program to incorporate new components

45. Questions? Questions???

46. Thank You