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Possible Electronics for Astro Part 2: Implementation

Gunther Haller Head, Research Engineering Department Particle and Astro Physics Division Stanford University/SLAC Oct 25, 2010. Possible Electronics for Astro Part 2: Implementation. Sidecar. Logical Electronics Architecture.

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Possible Electronics for Astro Part 2: Implementation

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  1. Gunther HallerHead, Research Engineering DepartmentParticle and Astro Physics Division Stanford University/SLACOct 25, 2010 Possible Electronics for AstroPart 2: Implementation

  2. Sidecar

  3. Logical Electronics Architecture • FIU: Focal-plane Interface Module consists of primary and redundant (cold-spare), tbd, FSIM Focal-plane Signal Interface Module • Includes power for NIR FSIM Function: Signal fan- out and fan-in plus plus fowler processing for NIR plus guider ICU Dataflow Function: Receive data stream from FSIM, extract, store in Flash Memory modules (tbd) transmit to spacecraft during ground contact, tbd ICU includes thermal control circuits

  4. Focal-Plane Signal Interface Module (FSIM) Block Diagram No redundant ICU for ASTrO 28 for ASTrO

  5. Transmit using Cold-Spare UTMC LVDS Drivers • Use UTMC cold-spare LVDS transmitters warm cold Prime FSIM Cold-Spare Transmitter FPGA FPM FPGA Redundant FSIM Cold Spare Transmitter • When redundant board is not powered, primary (powered) board drives signal to FPM. Redundant driver output is high-impedance (and vice-versa) • Made especially for space applications where primary and redundant drivers drive a single target

  6. FSIM Operation: SDI Fan-Out and Fan-In • Control/Clk received from ICU (via LVDS receiver) is received by FPGA • Protocol as described by ICU Protocol document 00227 • Basically is SIDECAR protocol with additional SIDECAR compliant header telling FSIM what to do with subsequent command. Single-cast, multi-cast, broadcast all naturally supported (need multi-cast to talk to e.g. all NIR’s but not CCD’s) • 40 FPGA outputs used to transmit command to 40 front-ends (via LVDS drivers) 20 total 1 total 2-pairs each Clock & Data to 40 FP modules Clock & Data from Primary ICU UTMC LVDS TX UTMC LVDS RX 2-pairs each FPGA Clock & Data from Redundant ICU UT54LVDM055LV Dual Driver and Receiver Low Voltage Differential Signaling (LVDS) Technology Two drivers and two receivers with individual enables >400.0 Mbps (200Hz) switching rates +/-340mV differential signaling, 3.3V power Cold spare all pins 18-lead dual in-line flatpack Available to SMD 5962-06202, QML Q and V compliant, 300K rads (Si) to 1MRAD • Fan-In of register read-back signals from FP modules similar, just drivers are replaced by receivers and receivers are replaced by drivers (not shown) • 200 ohm termination on each prim/red input to yield 100 ohm

  7. FSIM Enclosure • Solid Edge • Boards separated by aluminum structure to separate primary and redundant electronics • Thermal contact to box simple, set of screws. No components on back side • Mechanical (vibration) straight forward • Thermal & Structural analysis performed in UGS Velocity Series FEMAP v9.3 with NX NASTRAN Aluminum Separator Primary and Redundant FSIM Board if not single string

  8. Front-View FSIM Enclosure • Sheet metal for EGSE/prototype • Al for flight

  9. FSIM Board

  10. FSIM for AstrO • FSIM is implemented for 16 NIR/16 CCD, NIR has 4 data lines versus CCD only 1 • Modification: • bigger board connector for additional lines, add some LVDS Tx/Rx • FPGA code, logic different • Due to different size of Bright star windows Sidecar firmware on different Sidecar modules may got out of sync by few clock cycles, need to redesign FSIM input interface to decode all channels independently and think them later for simultaneous memory storage? • 2 FPGA in CG624 (with 418/each usable IOs) will be required. It is using now about 700 IOs all together in current design. Design is IO limited. The bigger package CD1152 for same device has 684 usable IOs and can be still too small. • One FPGA which deal with 16 NIR can stay almost same way to serve 14 FEs. The second FPGA could handle the second half of detectors (instead of CCD). Same connectors on box, on board we need bigger connectors since NIR has more data lines per detector than CCD.

  11. Instrument Control Unit • ICU contains (all cPCI modules) • Instrument Communication Module (ICM) • Transmits serial command protocol received via cPCI from CPU • Receives read-back data and forward via cPCI to CPU • Receives science data, preprocess capability (see later), forward to CPU for compression • BAE RAD750 CPU • Control/processing • Flash Memory Module • 128 Gbyte of Flash on single 6u module. (can partially load) • CPU puts compressed science data into flash, plus engineering data & tracker data, All already available by CPU • ICM (again, only one ICM in ICU (same as above)) • Receives science data from Flash-memory (via CPU or direct DMA) • Transforms data and generates I, Q signal for transmitter • MIL1553 board (from GLAST) includes EEPROM • Power supply board (from GLAST) Compressed NIR data Guider data Inst engineering data KA band transmitter on spacecraft side Or BATC PIB tbd ICM Flash Module 2 inputs: FSIM#1 prim. FSIM#1 redun.,. FPGA CPU Rx ICM Means cPCI bus

  12. Flash Memory Module • Started with cPCI module designed for GLAST • Use ACTEL FPGA with Actel cPCI IP core, SLAC FMC IP core • 128 Gbyte memory • 32 devices, each consists of 8-stack 4-Gbit Micron parts • 3D-Plus stack technology • NASA approved since 2001 • CNES/ESA approved since 2004 • On JPL flight part list since 2006 • More than 18,000 devices in orbit, another 20,000 ready to fly • Additional advantage since plastic flash parts can be hermetically sealed • Need flight-qualified flash memory chip lot • 4-Gbit Micron part which meets SNAP radiation specifications exists • Have full production lot purchased and in flight stores at SLAC • Note that cPCI memory boards are used for space missions • Used by e.g. spacecraft for EEPROM storage (picture not shown) • SLAC took cPCI flight module designed for GLAST and • Use flash instead of EEPROM • Instead of EEPROM memory controller IP, use SLAC FMC IP core in FPGA Typical 3D-Plus Stack

  13. SLAC Flash Memory Module Block Diagram

  14. SLAC Flash Memory Module, Frontside cPCI connectors Flight –equivalent ACTEL (is one-time programmable thus placed in socket for now so can replace) Commercial 4 Gbyte flash, replaced for flight by 3D-Plus 4-Gbyte Stack (same foot-print) V-Regulator Stiffener, Thermal Flight Front-Panel

  15. SLAC Flash Memory Module, Backside Buffers Wedge-locks

  16. Spacecraft Data Interface • Option A: send data to Payload Interface Board (LVDS, etc) • Option B: send data to transmitter (see next slide)

  17. ICM Block Diagram • Serial IO to FSIM • Same FPGA on ICM board does formatting/randomizing/RS to generate I/Q signal (or other interface if data goes to Payload Interface Board) • Clock on board is 150MHz oscillator, with programmable divide by 2’s for bad weather (75 MHz, 37.5 MHz, etc) (High f only needed if interface to transmitter) • Single source of clock for complete transmission • FPGA also generates 25-MHz system clock distributed via CDI to FSIM, etc Or to BATC PIB, tbd)

  18. ICM Spacecraft I-Q Generation (may not be needed, just FI) • Shown are spacecraft interface function blocks on ICM • Can handle CCSDS input source packets or raw science data (in that case it generates CCSDS packets • Has been coded in FPGA

  19. SLAC Instrument Communication Module • Front-panel connectors are only there for EGSE, for flight only use connections via backplane connector • cPCI to CDI serial interface conversion • Spacecraft Ka band transmitter interface (or BATC PIB interface) • Needs update of GLAST board, needs SC interface JDEM ICM with non-flight components Equivalent SLAC GLAST flight ICM

  20. ICU Crate (but needs mod from GLAST) • Partially loaded crate on left (without LCB and SIB) • Fully loaded crate on right • Shown are also serial card and ethernet cards, not part of flight assembly (cards with front-panel connections) • ASTrO mod: add slots for Flash and Temp boards • Box: make two slots bigger

  21. CBP & CPS & CPU CBP (Crate Backplane) For ASTrO need more slots CPS (Crate Power Supply Board) CPU (RAD750 from BAE)

  22. SIB & LCB SIB (Spacecraft MIL1553 and Storage Interface Board) assumes MIL1553 for ASTrO GLAST LCB (LAT Communication Board) for ASTrO need different FPGA, spacecraft interface

  23. Instrument Software (ISW) • Main Packages: GLAST Instrument Software Heritage • VXW - operating system and board support package • CDM - configuration database management • PBS - package basic OS services • MSG - task messaging • CCSDS – packet formatting • MIL1553- Mil1553 communication • New main JDEM packages for Instrument Software • SCBD – ICM Communications Board driver • Written, in use for EGSE and tests, need update • FMM – Flash Memory Module driver • Written, in use for EGSE, needs lots of testing • ICU – Modified control application – power, initialization, interface, etc • thermal control • ASTrO software for images, configuration of FSIM, managing of maps, summing/averaging, three types of acquistion • Compression

  24. Complete Signal Chain • Status: Each component in the signal chain from CRIC and SIDECAR to spacecraft IQ is functional ICU FSIM SNAP Serial Protocol Cables ICM FMM RAD750 CPU SIDECAR CRIC3 Passive Connector Adapter Board

  25. Detector/SIDECAR/ICU Image Readout • Image read out from detector with • SIDECAR using SNAP serial LVDS command protocol • No Teledyne JADE readout board used • Controlled/readout with PPC750 processor HyViSi Image SIDECAR Serial Protocol Cable Detector

  26. System Engineering: Power • Focal-plane Signal Interface Module (FSIM) • One FPGA, 7 SDRAM devices, PLL, LVDS drivers/receivers with driving terminations • Typical ~10 W, max over temperature ~20W (see appendix for details) including ~30% DC/DC converter inefficiency • Total of nominal ~0.35A, max ~0.7A @ 28V • Actual measurement with additional flight ACTEL estimate • Add power for 28 SIDECAR’s • Flash Memory Module • One FPGA, flash memories, clock buffer, data buffers • Typical 1W • Max over temperature: 5W • Total ICU, about 28 W • Essentially DC power, no large power variations • SDRAM are refreshed pipe-lined • FPGA activity pretty equal over time (most is clock-driven anyways in this design) • CPU has negligible (<2 W) variations as a function of activity • Flash module has essentially DC dissipation, only write in one block of devices at a time • Caution: Need to be careful with ACTEL power over temperature (likely box temp is )-40 to +60C, so Actel junction temperature can be 10’s of degrees higher depending on thermal resistance from junction to box. Need to size voltage regulators and DC/DC converters and fuses accordingly. Below is just stand-by current.

  27. Mass/Mechanical/Thermal • Mass • one FSIM board • 3 pounds • one FSIM box • 12 pounds, when same design used as GLAST • Thermal • Components only on one board side • Standard mount to box bottom plate with screws • Excellent thermal contact • See thermal analysis slides • Mechanical Analysis • Vibration analysis straight forward, simple box/construction • ICU • Mass

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