Compact Variability Modeling of Nanoscale CMOS Technology

1. Chi-Chao Wang, Yu (Kevin) Cao Compact Variability Modeling of Nanoscale CMOS Technology

2. - 2 - Compact Variability Modeling Process Variations in Light of Scaling Intrinsic and Manufacturing Variations Concluding Remarks

3. - 3 - Compact Variability Modeling Process Variations in Light of Scaling Intrinsic and Manufacturing Variations Concluding Remarks

4. - 4 - Approaching Physical Limits Many secondary effects are now critical: leakage, variations, reliability, manufacturability, ...

5. - 5 - Intrinsic Variations RDF, RTS, LER, Tox fluctuation, and their interactions! Approach: joint TCAD and compact modeling

6. Usually exhibit layout pattern dependence Approach: Compact modeling and in-situ characterization under various process and design conditions - 6 - Process Induced Variations

7. Compact Variability Modeling Turns �random� effects into systematic Prepares for design analysis and optimization - 7 -

8. - 8 - Compact Variability Modeling Process Variations in Light of Scaling Intrinsic and Manufacturing Variations Threshold voltage variation Layout dependent effects Concluding Remarks

9. - 9 - Vth Variation: RDF and LER Length scale: nm; random Approach: A SPICE-compatible gate-slicing method

10. Limitations on the Slicing Method Current distribution Fine for Ion if W >> L Slice width ~nm Linearity Ids should be a linear function of Vth Only Ion satisfies Ioff is not suitable - 10 -

11. - 11 - Modeling and Simulation Procedure Starting point: A non-rectangular gate shape with sL due to LER and sVth due to RDF Gate slicing at appropriate slice width Assignment of random Vth to each slice depending on its W, L, and sVth Sum the current together from each slice, then extract Vth variation from Ion ? Finish an equivalent transistor model for Vth variation under both RDF and LER

12. Validation with Atomistic Simulations A roughly 65nm technology Ion-based simulation method accurately predicts the variability of both Ion and Ioff under RDF Ioff-based extraction mis-predicts the distribution

13. Compact Modeling

14. Remaining Questions The dependence on device area maintains during the scaling But the slope is larger than RDF only model Possible reason: Tox variation and RTS Ongoing: an integral atomistic simulation and modeling for RDF+RTS+LER+Tox for technology optimization - 14 -

15. - 15 - Stress Induced Variation Length scale: ~100nm; layout dependent Approach: Physical modeling of layout dependence Systematic layout decomposition for efficient extraction

16. - 16 - Layout Dependence The layout dependence is captured by the peak and bottom stress levels in the piecewise-linear stress distribution

17. Mobility Enhancement Only five model parameters Scalable with various strain technologies - 17 -

18. Threshold Voltage Reduction Vth shift becomes larger at shorter channel length DIBL and sub-Vth swing is relatively insensitive to the stress effect - 18 -

19. - 19 - Rapid Thermal Annealing Length scale: ~mm; layout pattern density dependent Approach: Joint TCAD-compact modeling efforts

20. - 20 - Compact Variability Modeling Process Variations in Light of Scaling Intrinsic and Manufacturing Variations Concluding Remarks

21. Summary of Variations - 21 -

22. - 22 - Circuit Analysis with Variations Compact variability modeling: the key bridge between the fabrication and design communities Statistical circuit analysis: Accuracy: model of variations and the extraction method Computation efficiency: (model + solver) x simulation times