1 / 26

LOGIC DESIGN

LOGIC DESIGN. STATE REDUCTION STATE ASSIGNMENT (very limited in Mano, Roth more details). STATE REDUCTION ( DURUM İNDİRGEMESİ ). When should it be done After the state diagram determination What are the benefits Number of memory elements could be reduced

thi
Download Presentation

LOGIC DESIGN

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. LOGIC DESIGN STATE REDUCTION STATE ASSIGNMENT (very limited in Mano, Roth more details)

  2. STATE REDUCTION(DURUM İNDİRGEMESİ) • When should it be done • After the state diagram determination • What are the benefits • Number of memory elements could be reduced • Unused states introduced or their number increased which causes simplifications on the combinational part of the sequential design Ertuğrul Eriş

  3. EQUIVALENT STATE DEFINITION Different machine Z(A,X) =Z*(B,X) Same machine Z(A,X) =Z(B,X) A and B states are called «equivalent» if the output bit streams Z ve Z* are the same for any input in any lenght. Could this definition be used for testing whether two states are equivalent or not? Ertuğrul Eriş

  4. HOW TO FIND EQUIVALENT STATES • Teorem: Necessary and sufficient condition for A and B states being equivalent is • Next states should be equivalent • Outputs should be the same for all one-lenght inputs. • For example for a two-input-machine assume that z represents output functions, and g represents next state functions, then • zi(A,00) = zi (B,00) i=1,2 g (A,00) = g (B,00) • zi (A,01) = zi (B,01) i=1,2 g (A,01) = g (B,01) • zi (A,10) = zi (B,10) i=1,2 g (A,10) = g (B,10) • zi (A,11) = zi (B,11) i=1,2 g (A,11) = g (B,11) Ertuğrul Eriş

  5. PROOF • Teorem: Necessary and sufficient condition for A and B states being equivalent is • Next states should be equivalent • Outputs should be the same for all one-lenght inputs. • Assume that X:represent an input stream with any lenght • DEFINITION: Z(A, X )= Z(B, X) A=B • NECESSARY CONDITION • A=B Z(A, X )= Z(B, X) • Z(A, X )= Z(B, X) • Z(A, X X )= Z(B, X X) • Z(g(A), X )= Z(g(B), X) g(A)= g(B) • SUFFICIENT CONDITION • Z(A, X )= Z(B, X) • g(A)= g(B) Z(g(A), X )= Z(g(B), X) • Z(A, X )= Z(B, X) Ertuğrul Eriş

  6. STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent outputs should be the same for all one-lenght inputs. √ Ertuğrul Eriş

  7. STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE What would be the effect on sythesis? Ertuğrul Eriş

  8. STATE REDUCTION BY IMPLICATION TABLE EXAMPLE FOR MEALY MACHINE Ertuğrul Eriş

  9. STATE REDUCTION BY STATE PARTITIONING • Partition (bölmeleme) all the states • Put all the states which could be equivalent for all one-lenght inputs in the same class • Partition:union of the classes give the set of all states, while intersection is empty set • If two states are in the same calss then they could be equivalent • If two states are from two different classes then they will not be equivalent. Ertuğrul Eriş

  10. STATE REDUCTION EXAMPLE BY PARTITIONING • S0=(a b c d e f g) • z= 0 0 1 0 1 1 0 • S1 = ( c e f ) (a b d g ) • x=0 ( e c f ) (d f a b ) • x=1 ( d a b) (c g ea ) • S2 = ( c e f ) (b) (a d) (g) • x=0 ( e c f ) (f) (d a). (b) • x=1 ( d a b) (g) (c e) (a) • S3 = (c e) (f) (b) (a d) (g) • x=0 (e c) (f) (f) (d a). (b) • x=1 (d a) (b) (g) (c e) (a) • S3 = S4 Teorem: Necessary and sufficient condition for A and B states being equivalent is Next states should be equivalent outputs should be the same for all one-lenght inputs. Ertuğrul Eriş

  11. STATE ASSIGNMENT (DURUM KODLAMASI) • When shoud it be done • After state reduction • What are the benefits • State assignment will determine input functions of the memory elements and the output functions of the circuit in other words combinational part of the sequenttial circuit. • How many different codes are there? • n=number of state variables, then 2n codes • What is the number of different assignments? • m is the number of states • (2n) (2n-1) (2n-2) (2n-3)… (2n-m+1 )= Ertuğrul Eriş

  12. EQUIVALENT ASSIGNMENTS • 24 different assignments for a three-state machine • 1. and 3. column assinments are the interchange if state variables does not effect design cost, therefore equivalent assignments • 1. and 24. assinments are complement of each other, equivalent? Ertuğrul Eriş

  13. EQUIVALENT CODES/ASSIGNMENTS FOR VARIOUS FFs Ertuğrul Eriş

  14. EQUIVALENT ASSIGNMENTS FOR SEQUENCE DETECTOR Ertuğrul Eriş

  15. DIFFERENT ASSIGNMENTS FOR THREE AND FOUR STATE MACHINES Ertuğrul Eriş

  16. NUMBER OF STATES VS DIFFERENT ASSIGNMENTS Ertuğrul Eriş

  17. STATE ASSIGNMENTS METHODS • Boolean function complexity definition • Complexity definition for a group of functiions: not easy!! • Function which has less number of independen variables • Function which has either low number of one’s (zero’s) or high number of ones (zeros) • Increase number of first order cubes • Number of states =number of FF; codes are 2n Diğer yöntemler • Heuristic methods • Bench marking Ertuğrul Eriş

  18. A SIMPLE METHOD • RULE 1: Give neighbour codes for state pairs which goes to the same next states under the same inputs • RULE 2: Give neighbour codes for next state pairs four the neighbour codes • RULE 3: Give neighbour codes for state pairs which gives the same output for the same input Ertuğrul Eriş

  19. EXAMPLE Ertuğrul Eriş

  20. EXAMPLE • RULE 1: Give neighbour codes for state pairs which goes to the same next states under the same inputs • x=0: ACEG→AC AE AG CE CG EG; DF • x=1: ABDF→AB AD AF BD BF DF ; EG • RULE 2: Give neighbour codes for next state pairs four the neighbour codes • BC CD BE CFx2BGx2 • RULE 3: Give neighbour codes for state pairs which gives the same output for the same input • (ABCDEGG) (ABCDEF) • Neighbour coding pairs ordering: DF; EG; CF; BG; AE; AC; AB; AD Ertuğrul Eriş

  21. EXAMPLE Neighbour coding pairs ordering : DF; EG; CF; BG; AE; AC; AB; AD Ertuğrul Eriş

  22. EXAMPLE Ertuğrul Eriş

  23. PROGRAM DESIGN DEPT, PROGRAM G R A D U A T E S T U D E N T STUDENT P R OG R A M O U T C O M E S PROGRAM OUTCOMES P R OG R A M O U T C O M E S STATE, ENTREPRENEUR FIELD QALIFICATIONS EU/NATIONAL QUALIFICATIONS KNOWLEDGE SKILLS COMPETENCES NEWCOMERSTUDENT ORIENTIATION GOVERNANCE Std. questionnaire ALUMNI, PARENTS ORIENTIATION STUDENT PROFILE Std. questionnaire FACULTY NGO STUDENT, ??? CIRCICULUM ??? INTRERNAL CONSTITUENT Std. questionnaire EXTRERNAL CONSTITUENT EXTRERNAL CONSTITUENT REQUIREMENTS EU/NATIONAL FIELD QUALIFICATIONS PROGRAM OUTCOMES QUESTIONNAIRES QUALITY IMP. TOOLS GOAL: NATIONAL/INTERNATIONAL ACCREDITION

  24. BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001) !!Listening !! Doesn’t exits in the original!!! http://www.learningandteaching.info/learning/bloomtax.htm Ertuğrul Eriş

  25. ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ BLOOMS TAXONOMY Ertuğrul Eriş

  26. COURSE ASSESMENT MATRIX LEARNING OUTCOMES Ertuğrul Eriş

More Related