1 / 36

STEREO IMPACT POWER SUPPLIES

STEREO IMPACT POWER SUPPLIES. Peter Berg, UC Berkeley Space Sciences Lab, pcb@ssl.berkeley.edu , (510) 643-9443. SPECIFICATION EXTRACT. CONTROLLING DOCUMENTS. IMPACT/PLASTIC Power Converter Requirements. Performance Assurance Implementation Plan.

tilden
Download Presentation

STEREO IMPACT POWER SUPPLIES

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. STEREO IMPACT POWER SUPPLIES Peter Berg, UC Berkeley Space Sciences Lab, pcb@ssl.berkeley.edu, (510) 643-9443 P.Berg

  2. SPECIFICATION EXTRACT P.Berg

  3. CONTROLLING DOCUMENTS • IMPACT/PLASTIC Power Converter Requirements • Performance Assurance Implementation Plan • STEREO EMC Control Plan and EMI PerformanceRequirements Specification, 7381-9030 P.Berg

  4. MASS AND POWER ESTIMATES P.Berg

  5. STEREO IMPACT HVPS (SIT) P.Berg

  6. STEREO SIT HVPS ETU P.Berg

  7. HVPS MULTIPLIER STACK P.Berg

  8. SIT HVPS ETU TEST DATA P.Berg

  9. HIGH VOLTAGE MANUFACTURING FLOW VISUALLY INSPECT AND ALCOHOL CLEAN PWB BAKE BOARD OVERNIGHT @ 60C LOAD SURFACE MOUNT LOW VOLTAGE PARTS LOAD THROUGH HOLE PARTS IN LOW VOLTAGE SECTION EXCEPT OUTPUT TRANSISTORS INSTALL SHIELDING WALLS INSTALL DRIVE TRANSISTORS, HEAT SINK AND BRACKET QA INSTALL STANDOFFS INSTALL FEEDBACK RESISTOR EPOXY WALLS TO BOX- BAKE 2HR @ 65C P.Berg

  10. HIGH VOLTAGE MANUFACTURING FLOW EPOXY MULTIPLIER TO BOARD – BAKE 2HR @ 65C INSTALL TRANSFORMER SILVER EPOXY OUTPUT FILTER CAPACITORS TO BOARD – BAKE 1 HR @ 100C INSTALL OUTPUT CABLES AND STAKE BEND HV DIVIDER RESISTORS SILVER EPOXY DIVIDER RESISTORS – BAKE 1HR @100C ELECTRICAL TEST CLEAN AND DRY OVERNIGHT QA STAKE SEAL GAPS TO PREPARE FOR POTTING ALCOHOL LEAK CHECK, THEN 1HR BAKE @ 50C VACUUM BAKE OVERNIGHT @82C TO OUTGAS P.Berg

  11. HIGH VOLTAGE MANUFACTURING FLOW STORE IN 55C OVEN WHILE MIXING POTTING VACUUM POT @60C POUR OUT POTTING AT NORMAL AIR PRESSURE, SIT FOR 4 DAYS CLEAN, REMOVE SEALING/MASKING STAKING COAT BOTTOM, SIT OVERNIGHT, THEN BAKE 24HRS @60C GLUE STACK PRESSURE DISPERSER TIE DOWN AND WEDGE COMPRESSION FIBER EPOXY KNOTS, CURE 2HR@ 60C ELECTRICAL TEST QA P.Berg

  12. LOW VOLTAGE FLIGHT MANUFACTURING FLOW VISUALLY INSPECT AND ALCOHOL CLEAN PWB COAT & CURE ELECTRICAL TEST BAKE BOARD OVERNIGHT @ 60C TORQUE LOAD SURFACE MOUNT PARTS QA LOAD THROUGH HOLE PARTS CLEAN QA INSTALL IN BOX ELECTRICAL TEST CLEAN STAKE & CURE P.Berg

  13. INTERFACES 12 3 2 4 1 +28V 11 +28V return 5 +28V(secondary) 17 Bias Return 16 Bias Voltage Digital Ground 7 14 VCC_A 1,8 2.5V 8 6 +5VD 13 +5.1VA 20 6 +5.1VA 15 +12.1VA 10 6 +12.1VA 9 18 -5.1VA 6 -5.1VA 19 21 -12.1VA 6 -12.1VA ANALOG GROUND Airborn M83513/04-C11N IDPU SIT HVPS SWEA P.Berg

  14. 49 SIT +6A 42 CENTRAL +5.1D 18 SIT +5A RTN 18 BIAS RTN 1 SEPT-NS ANA RTN 1 Spare 1 LET PWR RTN 50 SIT +5A RTN 43 BIAS RTN 33 SEPT-NS ANA RTN 2 +28V MAIN/OP HTR 26 LET PWR RTN 19 SIT -6A 19 LVPS TEMP SENSOR 2 SEPT-NS +5.6A 3 +28V MAIN/OP HTR 2 LET +13A 34 SEPT-NS +5.6A 4 Spare 27 LET +13A 51 SIT -6A 44 +28V OP HTR 3 Spare 5 +28V SURV HTR 3 LET +6A 20 SIT -13A 20 +28V OP HTR 35 Spare 6 +28V SURV HTR 28 LET +6A 52 SIT -13A 45 +28V OP HTR RTN 4 SEPT-NS DIG RTN 7 Spare 4 LET -6A 21 SIT -5.2D 21 +28V OP HTR RTN 36 SEPT-NS DIG RTN 8 CHASSIS 29 LET -6A 53 SIT -5.2D 46 +28V SURV HTR 5 SEPT-NS +2.6D 9 Spare 5 LET -13A 22 SIT +2.6D 22 +28V SURV HTR 37 SEPT-NS +2.6D 10 +28V MAIN/OP HTR RTN 30 LET -13A 54 SIT +2.6D 47 +28V SURV HTR RTN 6 SEPT-NS +5.3D 11 +28V MAIN/OP HTR RTN 6 LET +2.6D 23 SIT +3.4D 23 +28V SURV HTR RTN 38 SEPT-NS +5.3D 12 Spare 31 LET +2.6D 55 SIT +3.4D 48 Spare 7 SEPT-NS SEP STAR 13 +28V SURV HTR RTN 7 LET +3.4D 24 SIT +5.1D 24 Spare 39 SEPT-NS SEP STAR 14 +28V SURV HTR RTN 32 LET +3.4D 56 SIT +5.1D 49 Spare 8 SEPT-E ANA RTN 15 PWR HRNS SHLD 8 LET +5.1D 25 HET PWR RTN 25 Spare 40 SEPT-E ANA RTN 33 LET +5.1D 57 HET PWR RTN 50 Spare 9 SEPT-E +5.6A 9 CENTRAL ANA RTN 26 HET +13A 51 Spare 41 SEPT-E +5.6A 34 CENTRAL ANA RTN 58 HET +13A 10 Spare 10 CENTRAL +13A 27 HET +6A 42 Spare 35 CENTRAL +13A 59 HET +6A 11 SEPT-E DIG RTN 11 CENTRAL +6A 28 HET -6A 43 SEPT-E DIG RTN 36 CENTRAL +6A 60 HET -6A 12 SEPT-E +2.6D 12 CENTRAL -6A 29 HET -13A 44 SEPT-E +2.6D 37 CENTRAL -6A 61 HET -13A 13 SEPT-E +5.3D 13 CENTRAL -13A 30 HET +2.6D 45 SEPT-E +5.3D 38 CENTRAL -13A 62 HET +2.6D 14 SEPT-E SEP STAR 14 CENTRAL DIG RTN 31 HET +3.4D 46 SEPT-E SEP STAR 39 CENTRAL DIG RTN 63 HET +3.4D 15 SIT PWR RTN 15 CENTRAL +2.6D 32 HET +5.1D 47 SIT PWR RTN 40 CENTRAL +2.6D 64 HET +5.1D 16 SIT +13A 16 CENTRAL +3.4D 65 Spare 48 SIT +13A 41 CENTRAL +3.4D 17 SIT +6A 17 CENTRAL +5.1D SEP J12 A, LVPS OUTPUT J1, SEP INPUT J12 B, LVPS OUTPUT SEP P.Berg

  15. IDPU LVPS BLOCK DIAGRAM +12 VoltsInternal BUCK DOWN CONVERSION SOFT START INPUT FILTER S/C 28 +5 Volts Internal LDO 300 KHZ OSCILLATOR +5 Volts Internal 300 KHz, Internal +12 Volts Internal +5V SUPPLY, PWM TOPOLOGY BUCK DOWN CONVERSION +5 Volts Internal 2.5V 300 KHz, Internal 5V +12.8V ±12.8V SUPPLY,CURRENT FED TOPOLOGY +12 Volts Internal +5V Analog LDO TOPOLOGY +5 Volts Regulated -5V Analog 300 KHz, Internal -12.8V +12 Volts Internal 100V SUPPLY,RESONANT TOPOLOGY +0 to 100V +5 Volts Internal Sync P.Berg

  16. SEP LVPS BLOCK DIAGRAM +12 VoltsInternal BUCK DOWN CONVERSION SOFT START INPUT FILTER S/C 28 LDO +5 Volts Internal 300 KHZ OSCILLATOR +5 Volts Internal 300 KHz, Internal +12 Volts Internal ± 13 V ± 13V, ± 6VA SUPPLY, PWM TOPOLOGY +5 Volts Internal ± 6VA 300 KHz, Internal -5.2, +5VD 2.5V BUCK DOWN CONVERSION -5.2, +5 SUPPLY, PWM TOPOLOGY 2.5 3.3V BUCK DOWN CONVERSION 3.3V THIS SECTION IS REPEATED, SEPT NS AND SEPT E ±5.1,SUPPLY, PWM TOPOLOGY ±5.1 V 5.1 V +2.6V BUCK DOWN CONVERSION +5.1 SUPPLY, PWM TOPOLOGY 2.6 V P.Berg

  17. SWEA LVPS BLOCK DIAGRAM +12 VoltsInternal BUCK DOWN CONVERSION SOFT START INPUT FILTER S/C 28 +5 Volts Internal LDO 300 KHZ OSCILLATOR +5 Volts Internal 300 KHz, Internal +12 Volts Internal +28V SUPPLY, PWM TOPOLOGY 28V +5 Volts Internal 300 KHz, Internal +12 Volts Internal +5V SUPPLY, PWM TOPOLOGY BUCK DOWN CONVERSION +5 Volts Internal 2.5V 300 KHz, Internal 5V +12V +12 Volts Internal ±12V, ± 5V SUPPLY, PWM TOPOLOGY +5V +5 Volts Internal -5V 300 KHz, Internal -12V +12 Volts Internal 140V SUPPLY,RESONANT TOPOLOGY +0 to 140V +5 Volts Internal Sync P.Berg

  18. PLASTIC LVPS BLOCK DIAGRAM +12 VoltsInternal BUCK DOWN CONVERSION SOFT START INPUT FILTER S/C 28 +5 Volts Internal LDO 300 KHZ OSCILLATOR +5 Volts Internal 300 KHz, Internal +12 Volts Internal ± 5V, ±12V SUPPLY, PWM TOPOLOGY BUCK DOWN CONVERSION 2.5V +5 Volts Internal 300 KHz, Internal 5V +12.8V P.Berg

  19. HIGH VOLTAGE MANUFACTURING FLOW VISUALLY INSPECT AND ALCOHOL CLEAN PWB BAKE BOARD OVERNIGHT @ 60C LOAD SURFACE MOUNT LOW VOLTAGE PARTS LOAD THROUGH HOLE PARTS IN LOW VOLTAGE SECTION EXCEPT OUTPUT TRANSISTORS INSTALL SHIELDING WALLS INSTALL DRIVE TRANSISTORS, HEAT SINK AND BRACKET QA INSTALL STANDOFFS INSTALL FEEDBACK RESISTOR EPOXY WALLS TO BOX- BAKE 2HR @ 65C P.Berg

  20. SCHEMATICS P.Berg

  21. P.Berg

  22. IDPU P.Berg

  23. SEP P.Berg

  24. SWEA P.Berg

  25. PLASTIC P.Berg

  26. IDPU LVPS P.Berg

  27. SWEA P.Berg

  28. PLASTIC P.Berg

  29. SEP LVPS P.Berg

  30. STATUS SIT HV ETU BUILT AND DELIVERED IDPU LVPS BOX FABRICATED, ETU IN TEST SCHEMATICS MOSTLY COMPLETE P.Berg

  31. IMPACT UCB LVPS/HVPS Review CLOSURE STATUS (8/9/02) Action No. Action Item TITLE ORIGINATOR STATUS DATE CLOSED 1 HVPS Temperature test Brian King 2 SIT HVPS Grounding Shane Hynes 3 Potting material Harry Culver 4 Capacitive load testing Harry Culver 5 LVPS Soft Start Shane Hynes 6 LVPS Input Voltage Testing Harry Culver 7 Oscillation Protection Harry Culver 8 Loss of synchronization circuitry Harry Culver 9 Survival of 40V Harry Culver 10 IDPU LVPS Clarity Harry Culver 11 Add grounding jumpers Harry Culver 12 Terminate shields Harry Culver 13 Add capacitor Harry Culver 14 PLASTIC ripple requirements Shane Hynes 15 Grounding requirement for PLASTIC LVPS Ken Crocker PEER REVIEW RFAs RESPONSE TBDone TBDone Submitted Submitted Submitted Submitted Done Designed Designed Done Designed Designed Done Received Submitted P.Berg

  32. WHATS LEFT SIT HV ETU – RESOLVE ETU TEST ISSUES IDPU FINISH ETU TEST SIT, SEPT, PLASTIC –> LAYOUT, BUILD AND TEST ETUS P.Berg

  33. VERIFICATION PERFORM CE TESTS ON FINISHED ETUS P.Berg

  34. ETU DELIVERY SCHEDULE • IDPU DEC 30, 2002 • SEP JAN 30, 2003 • SWEA, FEB 28, 2003 • PLASTIC MAR 15, 2003 P.Berg

  35. P.Berg

  36. KNOWN ISSUES • SCHEDULE REVISE PRIORITIES, ADD MANPOWER • SITHVPS RESOLVE SPECIFICATIONS RESOLVE CONSUMPTION VS SYNC • PARTS ISSUES LONG LEAD TIMES ON HV MOX RESISTORS LTC1877 PWM METALIZATION P.Berg

More Related