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Recent Development of FinFET Technology for CMOS Logic and Memory

Recent Development of FinFET Technology for CMOS Logic and Memory. Chung-Hsun Lin EECS Department University of California at Berkeley. Outline. Why FinFET FinFET process Unique features of FinFET Mobility, workfunction engineering, corne r effect , QM, volume inversion Issues

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Recent Development of FinFET Technology for CMOS Logic and Memory

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  1. Recent Development of FinFET Technology for CMOS Logic and Memory Chung-Hsun Lin EECS Department University of California at Berkeley

  2. Outline • Why FinFET • FinFET process • Unique features of FinFET • Mobility, workfunction engineering, corner effect, QM, volume inversion • Issues • Recent FinFET Develop • Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET • Memory • DRAM, SONOS, SRAM • Conclusion NTUEE Seminar 2006/04/29

  3. ITRS 2001 Projection Technology Scaling Investment Better Performance/Cost Market Growth MOSFET Scaling The first transistor 1947 The Power5 microprocessor Same transistor design concept NTUEE Seminar 2006/04/29

  4. Scaling : Moore’s law • Technology Drivers • Reduced cost / function • Improved performance • Greater circuit functionality • Source: Intel NTUEE Seminar 2006/04/29

  5. G S Lg D Tox Gate Xj Source Drain Leff Nsub Substrate Bulk-Si MOSFET Scaling Issues • Leakage current is the primary barrier to scaling • To suppress leakage, we need to employ: • Higher body doping  lower carrier mobility, higher junction capacitance, increased junction leakage • Thinner gate dielectric  higher gate leakage • Ultra-shallow S/D junctions  higher Rseries Desired characteristics: - High ON current (Idsat) - Low OFF current courtesy of Prof. Kuroda Keio University NTUEE Seminar 2006/04/29

  6. Issues for Scaling Lg to <25 nm • VT variation (statistical dopant fluctuations) • Leakage • Incommensurate gains in Idsat with scaling • limited carrier mobilities • parasitic resistance NTUEE Seminar 2006/04/29

  7. Ultra-Thin Body Double Gate Gate TSi Source SOI Drain SiO2 TBOX Silicon Substrate Vg Gate 1 TSi Source SOI Drain Tox Gate 2 Advanced MOSFET Structures • Leakage can be suppressed by using a thin body NTUEE Seminar 2006/04/29

  8. Source Drain Buried Oxide Substrate Gate Gate Source Drain Tbody Gate Thin-Body MOSFETs • Control short-channel effects with Tbody • No channel doping needed! • Relax gate oxide (Tox) scaling • Double-Gate is even more effective • Scalable to 10nm gate lengths Ultra-Thin Body Double-Gate NTUEE Seminar 2006/04/29

  9. Qinv Gate Qdepl Bulk Qinv Gate Buried Oxide Substrate Thin-Body Electric Field Reduction • Reduced vertical field in DG and UTB • No doping = No Qdepl! • Expected to benefit: • Mobility • Gate Leakage NTUEE Seminar 2006/04/29

  10. Thin-Body MOSFETs • Control short-channel effects with Tbody • No channel doping needed! • Relax gate oxide (Tox) scaling • No channel doping needed!  Ion  Cload • Double-Gate is even more effective • Scalable to 10nm gate lengths • Potentially less Vt scatter (dopant fluctuation) • Improved mobility • Lower vertical electric field • No impurity scattering • Improved swing • Better control of SCE • Lower VT • No depletion or junction capacitance NTUEE Seminar 2006/04/29

  11. Tbody,UTB = 5nm Tbody,UTB < 5nm 50 35 25 18 Circuit level benefits • Thin body devices • Good control of SCE • Steep Sub-threshold swing • Higher Idsat • Lower Capacitance - No Cjunc and Cdepl • Better CV/I delay at lower power Source: Leland Chang NTUEE Seminar 2006/04/29

  12. Planar DG MOSFET Gate 1 S D Gate 2 Current flow Current flow S D Gate 2 Gate 1 Gate 2 Gate 1 D Current flow S Vertical DG MOSFET FinFET Double-Gate MOSFETs NTUEE Seminar 2006/04/29

  13. Drain Source Gate Drain Gate Source Gate Gate Source Drain Gate Source Multi-Gate FinFET Gate • Rotation allows for self-aligned gates • Layout similar to standard SOI FET Gate Drain Drain Planar DG-FET 90° Rotation FinFET NTUEE Seminar 2006/04/29

  14. FinFET Process Flow Si Fin Resist SiO2 BOX Poly SOI Substrate Fin Patterning Poly Gate Deposition/Litho NiSi Si3N4 Spacer Gate Etch Spacer Formation S/D Implant + RTA Silicidation NTUEE Seminar 2006/04/29

  15. FinFET Device Structure Source Gate Drain • All features defined by optical lithography and aggressive trimming NTUEE Seminar 2006/04/29

  16. 10nm FinFET TEM NiSi Poly-Si 220Å SiO2 cap Lg=10nm Si Fin BOX NTUEE Seminar 2006/04/29

  17. 10nm FinFET I-V • Dual N+/P+ poly gates: - Need VT control • Low DIBL NMOS: 120 mV/V PMOS: 71 mV/V • Good SCE despite thick Tox (27Å EOT) & Wfin (26nm) - Due to large S/D doping gradient & spacer thickness NTUEE Seminar 2006/04/29

  18. Short-Channel Effects • Acceptable DIBL and subthreshold slope down to below 20nm Lgate • Nearly ideal (60mV/dec) subthreshold slope at long Lgate • NMOS better than PMOS due to slower As diffusion NTUEE Seminar 2006/04/29

  19. <100> Drain Gate (110) Surface Source <110> Orientation • Rotation by 45º changes orientation from (110) to (100) • Intermediate rotation similar to (111) (110) (100) ~(111) (110) NTUEE Seminar 2006/04/29

  20. How Mobility Changes • By shifting away from (100): • e is degraded, h is enhanced • Can we benefit from changing the N/P ratio? NTUEE Seminar 2006/04/29

  21. Gate Delay • PMOS enhancement (20%) is larger than NMOS degradation (8%) • Net delay improvement • Trade off h and e • NOR: PMOS stack • h very important • Most improvement • NAND: NMOS stack • h less important • Least improvement Lgate=35nm h, e NOR Inv NAND (100) (111) (110) (100) NMOS (110) PMOS NTUEE Seminar 2006/04/29

  22. Source Gate Gate Drain Source Source Drain Drain Drain Source Optimized FinFET • Trade off layout area for performance (110) PMOS (100) NMOS NTUEE Seminar 2006/04/29

  23. FinFET Layout Area • Non-(100) orientation saves area • Higher PMOS Idsat reduces drawn W • 45º orientation is less area efficient for smaller W • These devices are small anyway…does it matter? • Use only in critical path? Inverter NTUEE Seminar 2006/04/29

  24. Hybrid-Orientation-Technology (HOT) • Super HOT: SOI version • DSB: bulk version NTUEE Seminar 2006/04/29

  25. VT: What CMOS Needs… • Need symmetrical VT’s for proper CMOS operation • Need low VT’s for speed Inverter Response VDD VIN= VTN VIN= VDD-VTP Output 0 VDD Input NTUEE Seminar 2006/04/29

  26. Gate Work Function • Single gate material • VTn = -VTp = 0.4V • N+/P+ Poly • VTn = -VTp = -0.2V • For low body doping, desired FM values are: ~ 4.5 eV for NMOS ~ 5.0 eV for PMOS • Need two separate work functions for NMOS and PMOS! NTUEE Seminar 2006/04/29

  27. Anneal time = 15m except for 900oC (15s) TMo = 15nm Molybdenum FMEngineeringby Ion Implantation • FM can be lowered by N+ implantation and thermal anneal DFM increases with • dose • energy (N segregates to SiO2 interface & forms Mo2N) P. Ranade et al., IEDM 2002 NTUEE Seminar 2006/04/29

  28. Lg=80nm, TSi=10nm Vds=0.05V Vt shift Mo-Gated FinFETs (PMOS) Y.-K. Choi et al., IEDM 2002 • |Vt|=0.2V for lightly doped body, and is adjustable • by N+ implantation • Alternative technique: • Full silicidication (NiSi) of n+/p+ Si gates • (J. Kedzierski et al., W. Maszara et al., Z. Krivokapic et al., IEDM 2002) Potential issues include: - dopant penetration - thermal stability - stress/adhesion - gate dielectric reliability NTUEE Seminar 2006/04/29

  29. Corner Effect in Triple or More Gates • Corner Effect • Different Vth at corner region • Significant subthreshold leakage current • Strong corner radius, body doping dependence B. Doyle et al., VLSI Tech., p. 133, 2003 NTUEE Seminar 2006/04/29

  30. D G S Corner Effect [1] Vg=0.2 V Vg=1 V z z y y 2D current density distribution 2D current density distribution • DESSIS 3-D device simulator • Ideal rectangular fin shape • Nsub=1e15cm-3 NTUEE Seminar 2006/04/29

  31. Corner Effect [2] • Nsub=5e18cm-3 z corner y Vg=0.2 V flat 2D current density distribution z y Vg=1 V 2D current density distribution NTUEE Seminar 2006/04/29

  32. 3D Simulation w/ Various Shape of Corner • Lg=1mm, Wsi=30nm, Hsi=30nm, Tox=1nm • R=0, 5, 10, 15m NTUEE Seminar 2006/04/29

  33. Short Channel Behavior • MG device with sharp corner shows better short channel behavior than the rounded corner NTUEE Seminar 2006/04/29

  34. Double-humps induced by cap transistor • 30x30nm structure, Tox=3nm, Lg=1mm, Nsub=5e18cm-3 • Cap transistor induced lower Vt is very significant. • It may attribute to thicker Tox, and more partial depleted. NTUEE Seminar 2006/04/29

  35. Volume Inversion [1] Gate Gate Gate Gate eDensity eDensity 6.1E+13 6.1E+13 5.3E+13 5.3E+13 T T 4.5E+13 4.5E+13 si si 3.6E+13 3.6E+13 2.8E+13 2.8E+13 2.0E+13 2.0E+13 15 -3 18 -3 N =10 cm N =10 cm sub sub Oxide Oxide The electron density distribution from the 3-D ISE device simulator. Volume inversion is significant in intrinsic channel SDG (left). NTUEE Seminar 2006/04/29

  36. Volume Inversion [2] • For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region. • The inversion charge (current) in the subthreshold region is proportional to Tsi. NTUEE Seminar 2006/04/29

  37. QM Surface Potential Correction • Undoped case NTUEE Seminar 2006/04/29

  38. I-V Verification • Model can predict both subthreshold and strong inversion region well. NTUEE Seminar 2006/04/29

  39. S/D Series Resistance Issue • S/D series resistance will degrade the performance of thin body device • Can be improved by the selective Si epitaxy raised S/D J. Kedzierski et al., IEDM 2001 NTUEE Seminar 2006/04/29

  40. Outline • Why FinFET • FinFET process • Unique features of FinFET • Mobility, workfunction engineering, corner effect, QM, volume inversion • Issues • Recent FinFET Develop • Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high-K FinFET, Strained FinFET, Bulk FinFET • Memory • DRAM, SONOS, SRAM • Conclusion NTUEE Seminar 2006/04/29

  41. Triple-Gate Transistor B. Doyle et al., VLSI Tech. 2003 NTUEE Seminar 2006/04/29

  42. Omega-Gate Transistor NTUEE Seminar 2006/04/29

  43. 5nm Nanowire FinFET NTUEE Seminar 2006/04/29

  44. Independent Gate FinFET • Control the threshold voltage • Ideal rectangular shape of Si fin NTUEE Seminar 2006/04/29

  45. Independent Gate FinFET NTUEE Seminar 2006/04/29

  46. Multi-Channel FinFET NTUEE Seminar 2006/04/29

  47. Metal Gate FinFET NTUEE Seminar 2006/04/29

  48. Metal-Gate FinFET • Vth adjustment • Improvement of Ion K.G. Anil et al., VLSI Tech. 2005 NTUEE Seminar 2006/04/29

  49. TiN/HfO2 FinFET • Vth adjustment • Reduce Gate leakage N. Collaert et al., VLSI Tech. 2005 NTUEE Seminar 2006/04/29

  50. Inverted T Channel (ITFET) • UTB + FinFET • Continuous effective width L. Mathew et al., IEDM 2005 NTUEE Seminar 2006/04/29

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