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The HLT- Read-Out Receiver Card

H-RORC. The HLT- Read-Out Receiver Card. H-RORC v2.0. Tasks. Receiving of the raw detector data via optical links Injecting the data into the main memory of the hosts of the HLT front-end processors Sending processed data out of the HLT Pre-processing the data in the FPGA

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The HLT- Read-Out Receiver Card

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  1. H-RORC The HLT-Read-Out Receiver Card

  2. H-RORC v2.0

  3. Tasks Receiving of the raw detector data via optical links Injecting the data into the main memory of the hosts of the HLT front-end processors Sending processed data out of the HLT Pre-processing the data in the FPGA Reformatting and reordering of the data

  4. Functionality RORC Core Xilinx Virtex4 LX40 FPGA Xilinx Platform PROM for configuration Xilinx LogiCORE PCI 66MHz/64bit 2 x half CMC interface to two DIU cards RORC X-tend • 4 x DDR-SDRAM 166/200 MHz up to 1Gb/module • PCI-X 133/64 • 2 x TagNET : fast serial full-duplex links • “secure remote configuration” with FLASH and CPLD • “Ready for Linux” (FAST-Ethernet, RS232, Flash memory)

  5. Core & X-tend Memory Configuration DDR-SD DDR-SD USER- FLASH XC95144 CPLD CMC-J11/J22 DDR-SD CFG- FLASH DDR-SD CMC-Connector CMC-Connector OSC Serial links XILINX VIRTEX4 LX40 RS-232 PLATFORM PROM ETH-PHY LVDS links Power 1V2 POWER Power 1V8 TAGNET OSC TAGNET Power 2V5 PCI-66/64 - PCI-X 133/64 PCI-Power 3V3

  6. Core only Memory Configuration DDR-SD DDR-SD USER- FLASH XC95144 CPLD CMC-J11/J22 DDR-SD CFG- FLASH DDR-SD CMC-Connector CMC-Connector OSC Serial links XILINX VIRTEX4 LX40 RS-232 PLATFORM PROM ETH-PHY LVDS links Power 1V2 POWER Power 1V8 TAGNET OSC TAGNET Power 2V5 PCI-66/64 - PCI-X 133/64 PCI-Power 3V3

  7. TOP VIEW

  8. BOTTOM VIEW

  9. Verification The following tests have been successfully performed : - JTAG - PCI-33/32, PCI-33/64, PCI-66/32, PCI-66/64 - CMC-Connectors with DIU/SIU cards - Xilinx Platform PROM for configuration - Configuration with Flash & CPLD - DDR-SDRAM - TagNET The H-RORC passed CERNs Production Readiness Review in October 2005.

  10. PCI DMA Write Performance Measured performance of DMA data cycles on the PCI bus. • Theoretical bandwidth of a 64bit/66MHz PCI bus: • 528 MByte/s max. 2xDIU data rate For each DMA block length 10/100/1000/10000 transactions have been performed. The time for each transaction was measured by a counter with a 15ns granularity. The transmitted data was checked for errors: No errors occurred

  11. Summary & Sources • The H-RORC is currently in production. • A preproduction batch of 15 boards was received and is currently under testing. • Schematics, Assembly and Bill of Materials can be found here • http://www.kip.uni-heidelberg.de/wiki/HLT/ • H-RORC PRR related changes : • 2 panel leds • JTAG chain connected to PCI • large capacitors removed from the backside to achieve PCI compliance • power consumption needs to be observed for each design but was no problem up to now • documentation is on the web

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