SAM7 Hardware Considerations

1. SAM7 Hardware Considerations Frederic BOYER AT91 Support Group. Version 1.0 October 2006

2. AT91SAM7 Power Supply Strategies • 3.3V Single Power Supply Strategy: On-chip Voltage Regulator Used • 1.8V & 3.3V Dual Power Supply Strategy: • On-chip Voltage Regulator not Used and ADC used. • On-chip Voltage Regulator and ADC not used.

3. AT91SAM7 Power Supply Strategies (cont.) 3.3V Single Power Supply (On-chip Voltage Regulator Used) : Decoupling Capacitors on all Power Supplies

4. AT91SAM7 Power Supply Strategies (cont.) • VDDIN: Voltage regulator Input and ADC (3.3V). • VDDIO: I/O lines (3.3V) and USB transceivers(SAM7S). • VDDFLASH: Flash (3.3V) andUSB transceivers(SAM7X/XC/SE). 3.3V Single Power Supply (On-chip Voltage Regulator Used) : VDDIN must be connected to a decoupling/filtering capacitor to improve start-up stability and reduce source voltage drop

5. AT91SAM7 Power Supply Strategies (cont.) • VDDOUT: Voltage regulator Output (1.8V). • VDDCORE: On-chip RC, Device and Flash logic (1.8V). • VDDPLL: Main Oscillator and PLL (1.8V). 3.3V Single Power Supply (On-chip Voltage Regulator Used) : VDDOUT must be connected to a decoupling/filtering capacitor to guarantee 1.8V stability

6. AT91SAM7 Power Supply Strategies (cont.) 3.3V & 1.8V Dual Power Supplies(On-chip Voltage Regulator NOT Used and ADC used): Decoupling Capacitors on all Power Supplies

7. AT91SAM7 Power Supply Strategies (cont.) • VDDIN: ADC Only(3.3V). • VDDIO: I/O lines (3.3V) and USB transceivers(SAM7S). • VDDFLASH: Flash (3.3V) andUSB transceivers(SAM7X/XC/SE). 3.3V & 1.8V Dual Power Supplies(On-chip Voltage Regulator NOT Used and ADC used): VDDIN must be connected to a decoupling/filtering capacitor to improve start-up stability and reduce source voltage drop

8. AT91SAM7 Power Supply Strategies (cont.) 3.3V & 1.8V Dual Power Supplies(On-chip Voltage Regulator NOT Used and ADC used): • VDDCORE: On-chip RC, Device and Flash (1.8V). • VDDPLL: Main Oscillator and PLL (1.8V). VDDOUT must be connected to a decoupling/filtering capacitor to prevent on-chip voltage regulator oscillations On-chip Voltage Regulator must be in Idle mode

9. AT91SAM7 Power Supply Strategies (cont.) 3.3V & 1.8V Dual Power Supplies(On-chip Voltage Regulator and ADC NOT Used): Decoupling Capacitors on all Power Supplies

10. AT91SAM7 Power Supply Strategies (cont.) • VDDIO: I/O lines (3.3V) and USB transceivers(SAM7S). • VDDFLASH: Flash (3.3V) andUSB transceivers(SAM7X/XC/SE). 3.3V & 1.8V Dual Power Supplies(On-chip Voltage Regulator and ADC NOT Used): VDDIO must be connected to a decoupling/filtering capacitor to improve start-up stability and reduce source voltage drop VDDIN connected to GND

11. AT91SAM7 Power Supply Strategies (cont.) 3.3V & 1.8V Dual Power Supplies(On-chip Voltage Regulator and ADC NOT Used): • VDDCORE: On-chip RC, Device and Flash (1.8V). • VDDPLL: Main Oscillator and PLL (1.8V). VDDOUT can be left unconnected VDDCORE must be connected to a decoupling/filtering capacitor to improve start-up stability and reduce source voltage drop

12. SAM7 Typical Power Supply Pins Configuration

13. SAM7 Power Supply Constraints • 3.3V Single Power Supply: • VDDCORE (so VDDIN) slope must be superior or equal to 6V/ms. SAM7S SAM7X • 3.3V & 1.8V Dual Power Supply: • VDDCORE slope must be superior or equal to 6V/ms. • VDDFLASH must always be superior or equal to VDDCORE. SAM7S SAM7X SAM7

14. Clock, Oscillator and PLL • Crystal (Main Oscillator in Normal Mode): XIN and XOUT • Main Oscillator range: 3 to 20 MHz. • Crystal Load capacitance to check (CCRYSTAL). • Internal Equivalent Load Capacitance (CL) is: • 11 pF (SAM7SE32). • 20 pF (other SAM7). • 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz.

15. Clock, Oscillator and PLL (cont.) • Crystal (Main Oscillator in Normal Mode): XIN and XOUT • The crystal load capacitance (CCRYSTAL) is the equivalent capacitor value that circuit must “show” to the crystal in order to oscillate at the target frequency. Cload = CCRYSTAL - CL • Example: CCRYSTAL = 20pF (SAM7S-EK, SAM7X-EK and SAM7SE-EK) • AT91SAM7SE32: 18pF external capacitors are required on XIN and XOUT. External capacitor  2*Cload = 2*(CCRYSTAL - CL) = 2*(20-11) = 18pF • Other AT91SAM7: no need to add external capacitors. (Cload = 0pF).

16. Clock, Oscillator and PLL (cont.) • External Clock (Main Oscillator in Bypass Mode): XIN • External Clock Range: up to 50 MHz. • Duty Cycle: 40-60% • 1.8V Square Wave signal (VDDPLL). XOUT can be left unconnected

17. Clock, Oscillator and PLL (cont.) • PLL Filter: PLLRC pin • PLL Filter calculation tool. • ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx.xls • 3 Values necessary to compute the correct filter: • Fin: Quartz Frequency • MUL: PMC Multiplier (MUL+1) • DIV: PMC Divider (DIV) • Adjust R-C1-C2 for startup time. If PLL not used, PLLRC can be left unconnected

18. ICE & JTAG • TDI, TCK, TMS and TDO: No internal Pull-up resistors. • Pull-up on TDI, TCK, TMS to reduce power consumption.

19. ICE & JTAG (cont.) • JTAGSELpin: Internal Pull-down resistor (15 kOhm). • JTAGSEL=0 (Default value): JTAG/ICE interface selected. Can be left unconnected for normal operations. • JTAGSEL=1 : must be tied to VDDIO to enter JTAG Boundary Scan.

20. ERASE pin • Internal Pull-down resistor (15 kOhm). • ERASE=0 (Default value): no action. Can be left unconnected for normal operations. • ERASE=1 : must be tied to VDDIO to erase: • Flash content • GPNVM bits • Security Bit • Debouncing Time (On-chip RC): • SAM7S: none (4µs) • SAM7X/XC: 200 ms • SAM7SE: 220 ms

21. Reset • POR (Power On Reset) on VDDCORE • Reset the whole system. • RESET (NRST pin) • NRST is configured as output at power-up. • Internal Pull-up resistor on VDDIO for User/External Reset control: • SAM7S/X/XC: 10 kOhm • SAM7SE: 100 kOhm Can be left unconnected. No constraints on the reset pulse length (Built-in POR)

22. TST pin • Internal Pull-down resistor (15 kOhm) • TST=0 (Default value): no action. Can be left unconnected for normal operations. • TST=1 : Product dependant Must be tied to VDDIO to enter: • FFPI mode (PA0=PA1=1 and PA2=0) • Or SAM-BA Boot recovery mode (PA0=PA1=PA2=1)(only for SAM7S).

23. PIO • I/O Lines • Pulled-up Input at reset: • SAM7S/X/XC: 10 kOhm • SAM7SE: 100 kOhm • 4 High drive current I/O lines (16mA)Other I/O lines: 8mA • 5V tolerant (SAM7S/X/XC only) • Schmitt trigger inputs (SAM7SE only) • Unused I/O: Should be configured as output driven at ‘0’, pull-up disabled to reduce power consumption.

24. ADC If the ADC Controller is not used: • ADVREF • AD4 • AD5 • AD6 • AD7 Should be connected to GND to reduce power consumption. Pure Analog Inputs

25. USB (SAM7S/X/XC) • No Internal Pull-up: external circuitry necessary to enable the pull-up. • No Internal Pull-down. • Host disconnected  DDP must be disconnected (self powered design)  DDP and DDM are floating  Over consumptionSolution: 330 kOhm pull-down on DDP and DDM to reduce over consumption. • Built-in Transceiver Enabled by default: may be disabled to reduce power consumption. VBUS monitoring circuitry necessary to remove the pull-up when the host switches off

26. USB (SAM7SE) • Internal Pull-up: 1.5 kOhm pull-up (disabled by default):No need for an external pull-up circuitry ! • No Internal Pull-down. • Host disconnected  DDP must be disconnected (self powered design)  DDP and DDM are floating  Over consumptionSolution: 330 kOhm pull-down on DDP and DDM to reduce over consumption. • Built-in Transceiver Disabled by default. VBUS monitoring circuitry necessary to remove the pull-up when the host switches off

27. USB If the USB Device Controller is not used, to reduce power consumption: • DDP must be: • Tied to VDDIO (SAM7S). • Tied to VDDFLASH (SAM7X/XC). • Left floating (SAM7SE). • DDM must be: • Tied to GND (SAM7S/X/XC). • Left floating (SAM7SE). .

28. SDCK pin (SAM7SE only) • SDCK (SDRAM Clock) • SDCK is tied low after reset. • Output-only without pull-up and not 5V-tolerant • Maximum Output Frequency: • 48.2 MHz for VDDIO from 3.0V to 3.6V • 25 MHz for VDDIO from 1.65V to 1.95V SAM7SE Only !