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ME 4447/6405 Pulse Width Modulation (PWM )

Adam Becker Matt Eicholtz Jie Gong Dustin Li. ME 4447/6405 Pulse Width Modulation (PWM ). Outline. Applications Analog vs. Digital Actuation Linear amplifier drawbacks Efficiency Pulse Width Modulation How it works Choosing the correct PWM Frequency Implementing PWM on the MC9S12C32.

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ME 4447/6405 Pulse Width Modulation (PWM )

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  1. Adam Becker Matt Eicholtz Jie Gong Dustin Li ME 4447/6405Pulse Width Modulation (PWM)

  2. Outline • Applications • Analog vs. Digital Actuation • Linear amplifier drawbacks • Efficiency • Pulse Width Modulation • How it works • Choosing the correct PWM Frequency • Implementing PWM on the MC9S12C32

  3. Applications • Telecommunications • RC devices • Audio effects • Power delivery • Voltage regulation • Amplification • Example: • Interfacing with actuators

  4. Interfacing with Actuators • Microcontrollers control electrical power through actuators • Requirement: a drive to take commands and control power • Result: effects mechanical part of system • Form of commands vary • From signals proportional to desired electrical • To industrial ethernet and wireless protocols • Microcontroller • Decision making • Communication (low power) • Drive • Power amplifier • Actuation (high power) • Actuator • Power conversion

  5. Linear Power Amplifiers Possibly inefficient Digital comm. (low power) K Analog Signal (low power) Actuation (high power) Microcontroller Digital to Analog Converter Linear Amplifier Actuator Sensitive to noise • Purpose: • Convert low power analog signals to high power • Notes: • Analog signals are sensitive to noise • Linear amplifiers may be inefficient

  6. Digital Power Amplifiers Digital comm. (low power) On-Off actuation (high power) Microcontroller MOSFET (or similar) Actuator How does on-off actuation provide varying response? • Purpose: • Convert low power digital signals to high power • Notes: • Transistors operating in saturation region can be very efficient

  7. Pulse Width Modulation (PWM) Off Time On Time Period ~33% Duty Cycle On Time Period Duty Cycle = ~67% Duty Cycle Actuation is varied by controlling the percentage of “on” time for the signal

  8. Duty Cycle • The average value of a PWM signal increases linearly with the duty cycle

  9. Choosing your PWM frequency • Many actuators exhibit a low pass filter response Second order low pass filter

  10. Choosing your PWM frequency Input signal (PWM) Output signal (actuator response)

  11. Choosing your PWM frequency • Low frequencies can cause ripple as seen previously... upper bound? • Resolution: inversely proportional to the number of distinct duty cycles you can generate for a given frequency/period • Transitions can only occur on a clock tick • Frequency limited by your clock and desired resolution

  12. Choosing your PWM frequency • Example: 8 MHz clock, choose PWM to be 4 MHz • Limited resolution: only 3 duty cycles to choose from

  13. Choosing your PWM frequency • Additional upper bound: high frequency current in actuator coils can induce eddy currents, resulting in motor heating and reduced efficiency. Loss is proportional to frequency squared.(Heathcote, Martin (1998-11-03). J & P Transformer Book, Twelfth edition. Newnes, pp. 41–42. ISBN 0750611588.) • Human hearing range ~ 20 Hz - 20 kHz • Summary: avoid ripple, resolution loss, power loss, and human hearing

  14. Implementing PWM using the MC9S12C32 Six independent channels 8- or 16-bit resolution Individual polarity and alignment settings

  15. PWME $00E0 Example: Enable 2 8-bit channels, 1 16-bit channel LDAA #$0BSTAA $00E0 *sets pin 0,1, and 3 (make sure CON23 = 1) PWMEx: Enable (1) or Disable (0) PWM channel x

  16. PWMPOL $00E1 PPOLx: PWM output starts high then goes low when duty count is reached (1) or starts low and goes high when duty count is reached (0)

  17. PWMCNT0 $00EC Contains the count value for PWM channel 0. In left aligned mode, the counter counts from 0 to the value in the period register-1. In center aligned mode, the counter counts from zero to the value in the period register-1 and then back down to zero. Any write to the register causes the value to be reset to #$00 and the counting procedure is restarted. See also PWMCNT1-5 ($00ED-$00F1)

  18. PWMPER0 $00F2 • Determines the PWM period for channel 0. • Left aligned output (CAE0=0) PWM0 period = channel clock period * PWMPER0 • Center aligned output (CAE0=1) PWM0 period = channel clock period * (2*PWMPER0) • See also PWMPER1-5 ($00F3-$00F7)

  19. PWMDTY0 $00F8 • Determines the PWM duty cycle for channel 0. • Polarity=0 (PPOL0=0) Duty cycle = [(PWMPER0-PWMDTY0)/PWMPER0] * 100% • Polarity=1 (PPOL0=1) Duty cycle = [PWMDTY0 / PWMPER0] * 100% • See also PWMDTY1-5 ($00F9-$00FD)

  20. PWMCAE $00E4 CAEx: PWM channel x configured for Center- (1) or Left-Aligned (0) output

  21. Left vs. Center Aligned

  22. Resolution Concerns • Although the PWM subsystem in the MC9S12C32 is said to be 8-bit, the resolution in practice will depend on the value in PWMPERx • The number of distinct duty cycles equal to the value stored in PWMPERx • Max when PWMPERx = #$FF (28=256 distinct duty cycles, 8-bit resolution)

  23. Determining Clock Source Clock SA (or SB) Bus Clock Clock A (or B) PWMPRCLK PWMSCLA There are four possible clock sources for the PWM channels, each of which is derived from the bus clock, clocks A, SA, B and SB Clocks A and B are derived by applying a prescaler to the bus clock (see PWMPRCLK) Clocks SA and SB are derived by applying a prescaler to clocks A and B (see PWMSCLA and PWMSCLB)

  24. PWMCLK $00E2 PCLK5: Clock SA (1) or clock A (0) is the clock source for PWM5 PCLK4: Clock SA (1) or clock A (0) is the clock source for PWM4 PCLK3: Clock SB (1) or clock B (0) is the clock source for PWM3 PCLK2: Clock SB (1) or clock B (0) is the clock source for PWM2 PCLK1: Clock SA (1) or clock A (0) is the clock source for PWM1 PCLK0: Clock SA (1) or clock A (0) is the clock source for PWM0

  25. PWMPRCLK $00E3 PCKB[2:0]: Prescaler for Clock B PCKA[2:0]: Prescaler for Clock A

  26. PWMSCLA $00E8 The contents of PWMSCLA are used to determine the frequency of Clock SA as: Similarly, PWMSCLB determines the frequency of Clock SB

  27. PWMCTL $00E5 • CONxy: channels x and y are separate 8-bit channels (0) or are concatenated to form one 16-bit channel (1). X forms the high byte and y forms the low byte. Note: 1. Change these bits only when both corresponding channels are disabled. • Resolution: three 16-bit channel (compared with six 8-bit channel ) 3. Channel y determines the configuration. • PSWAI: The clock to the prescaler stops (1) or continues (0) in wait mode • PFRZ: PWM counters stop (1) or continue (0) while in freeze mode (this is useful for emulation)

  28. Summary of Features Six independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffered. Changes takes effect when the end of the effective period is reach or when the channel is disabled. Programmable center or left aligned outputs on individual channel Six 8-bit channels or three 16-bit channels PWM resolution Four clock sources (A, B, SA and SB) provide for a wide range of frequencies Programmable clock select logic Emergency shutdown

  29. Example: Configuring a PWM channel • Frequency: 40 kHz • Period = 1/Frequency = 25μs • Duty Cycle = 50% • To choose clock source, consider resolution of PWM • Number of distinct duty cycle values is equal to the PWM period in clock cycles • Bus clock period is 125 ns  200*125ns = 25μs • Since 200 < 255, we can use clock A with a prescaler=1 • Left aligned output

  30. Example: Configuring a PWM channel PWMCLK = #$00 - PWM0 uses clock A PWMPRCLK = #$00 - Prescaler = 1 PWMPOL = #$01 - Positive polarity PWMCAE = #$00 - Left aligned PWMPER0 = #$C8 - Period = 200 PWMDTY0 = #$64 - Duty cycle = 100/200 = 50% PWME = #$01 - Enable PWM channel 0

  31. Assembly Code PWME EQU $00E0 PWMCAE EQU $00E4 PWMDTY0 EQU $00F8PWMPER0 EQU $00F2 PWMPOL EQU $00E1 PWMCLK EQU $00E2 PWMPRCLK EQU $00E3 ORG $1000 LDAA #$00 STAA PWMCLK ;Use Clock A STAA PWMPRCLK ;Clock A prescaler = 1 STAA PWMCAE ;Left aligned output LDAA #$01 STAA PWMPOL ;Positive polarity (starts high) LDAA #$C8 STAA PWMPER0 ;Period = 200 (25μs) LDAA #$64 ;100 decimal STAA PWMDTY0 ;Duty cycle = 50% (100/200) LDAA #$01 STAA PWME ;Enable PWM Channel 0 ...

  32. C Code // Setup chip in expanded mode MISC = 0x03; PEAR = 0x0C; MODE = 0xE2; TERMIO_Init(); // Init SCI Subsystem EnableInterrupts; PWMPER0 = 200; // set PWM period (125 ns * 200 = 25 us = 40 kHz) PWMDTY0 = 100; // set initial duty cycle (100/200 = 50%) // setup PWM system PWMCLK_PCLK0 = 0; // set source to clock A PWMPRCLK_PCKA0 = 0; // set prescaler for clock A = 1, so clock A = bus clock PWMPRCLK_PCKA1 = 0; PWMPRCLK_PCKA2 = 0; PWMCAE_CAE0 = 0; // "left aligned" output PWMPOL_PPOL0 = 1; // set duty cycle to indicate % of high time PWMCNT0 = 0; // write to counter to make changes take effect PWME_PWME0 = 1; // enable PWM 0

  33. Example 2: Configuring PWM channels CHANNEL 2-3 (16-bit) • Frequency: 50 kHz • Period = 1/Frequency = 20μs • Duty Cycle = 60% • To choose clock source, consider resolution of PWM • Number of distinct duty cycle values is equal to the PWM period in clock cycles • Bus clock period is 125 ns  160*125ns = 20μs • Since 160 < 255, we can use clock B with a prescaler=1 • Left aligned output CHANNEL 0 (8-bit) • Frequency: 10 kHz • Period = 1/Frequency = 100μs • Duty Cycle = 30% • To choose clock source, consider resolution of PWM • Number of distinct duty cycle values is equal to the PWM period in clock cycles • Bus clock period is 125 ns  800*125ns = 100μs • Since 800 > 255, we can use clock A with a prescaler=4 • Now, PWMPER0 = (100μs/(4*125ns) = 200 • Left aligned output

  34. Example 2: Configuring PWM channels PWMCLK = #$00 – PWM0 uses clock A, PWM2-3 uses clock B PWMPRCLK = #$20 - Prescaler (clock A) = 1 Prescaler (clock B) = 4 PWMPOL = #$09 - Positive polarity PWMCAE = #$00 - Left aligned PWMPER0 = #$C8 - Period = 200 PWMDTY0 = #$3C - Duty cycle = 60/200 = 30% PWMPER3 = #$A0 - Period = 160 PWMDTY3 = #$60 - Duty cycle = 96/160 = 60% PWME = #$09 - Enable PWM channel 0,3

  35. C Code // Setup chip in expanded mode MISC = 0x03; PEAR = 0x0C; MODE = 0xE2; TERMIO_Init(); // Init SCI Subsystem EnableInterrupts; PWMPER0 = 200; // set PWM period (125 ns * 4 * 200 = 100 us = 10 kHz) PWMDTY0 = 60; // set initial duty cycle (60/200 = 30%) PWMPER3 = 160; // set PWM period (125 ns * 160 = 20 us = 50 kHz) PWMDTY3 = 96; // set initial duty cycle (96/160 = 60%) // setup PWM system PWMCLK = 0; // set source to clock A PWMPRCLK = 32; // set prescaler for clock A = 1, so clock A = bus clock // set prescaler for clock B = 4 PWMCAE = 0; // "left aligned" output PWMPOL= 9; // set duty cycle to indicate % of high time PWMCNT0 = 0; // write to counter to make changes take effect PWMCNT3 = 0; // write to counter to make changes take effect PWME = 9; // enable PWM 0 and PWM 3

  36. References • ME 4447/6405 PWM Lecture • MC9S12C Family, MC9S12GC Family Reference Manual (pp. 347-382)

  37. Questions?

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