1 / 6

Design For Testability Supplied By Vayoinfo

Design For Testability (DFT) is an expert in the SOC design cycle, which facilitates a design for detecting production defects. With the increase in size & complexity of chips, assisted by the progression of manufacturing technical advancement, It has evolved as a expertise in itself over a period of time. DFT Engineers, works on presenting various test components as part of the design flow, to improve the testability of logic, pads, memories, interconnects. For design for testability contact to vayoinfo @ http://www.vayoinfo.com/design-for-testability/<br>

vayoinfo
Download Presentation

Design For Testability Supplied By Vayoinfo

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Design for Testability Towards Industry 4.0 & IoT intelligent software, pleasant work www.vayoinfo.com

  2. Are you always willing to stay with those issues? Quality defects, reliability issue, process headache, business risk Design Equipment programming 1 4 • Wrong polarity, location offset, inline fine- tune, … • Lower test coverage, lower utilization, … No thermal consideration, small annual ring small, silkscreen error, Silkscreen incomplete, … >30% PCB design comes with problem. • • Manufacturing NPI cycle 2 5 • Frequent prototyping, high cost • Long cycle, impact time to market, … Short, open, tombstone, cold sold, Void, … >60% defects could be found prior to build • • 3 6 Post sales Process design sold joint crack, sold joint peeloff, … Repair rate for consumer product: 5%~37% in initials 3 years • Difficult to transfer knowledge • No effective tool to continually improve process capability • … • • IPC research: 80% defects could be found and resolve during NPI stage.

  3. Change from NPI Past Yesterday Today Vayo customer solved this issue. They may still happen at your side. Above issues puzzles most of us. Ex.: Intel/Venture/SurfaceArt/Bosch… Intelligent Vayo NPI software makes manufacturing more agile and smart!

  4. Company introduction  Founded on Jan of 2005, headquarter in China/Shanghai;  Dedicates to intelligent NPI software to accelerate design to manufacturing;  Fully in-house development, owns copyrights and patents;  Product installed >20 countries and regions worldwide;  Strategy partnership with equipment and EDA provider: Keysight/ViTrox/TRI/Fuji/Panasonic/Altium… >10 years dedication on NPI technology brings up the world-class product.

  5. Core product: Intelligent NPI software for PCBA Reduce design & mfg cycle: 30%-70% Reduce quality defects: 30%+ Increase reliability: 30%+ Increase design and mfg efficiency: 40%+ Reduce design and mfg cost: 20% +      Intelligent DFx analysis DFM Expert & DRC+ PCB layout Eng., process Eng. NPI Eng. Process Eng., Industry Eng. Debug tech, others… Testing Eng. SMT programmer Document Expert SMT Expert/ Accelerator Other NPI sw Test Expert Fast placement programming, support Fuji, Panasonic, ASM, Juki, Yamaha… Board troubleshooting, Gerber conversion, assembly drawing, NPI team collaboration DFT/Testability, ICT/FP/AXI/AOI programming Work instruction document preparation * NPI：New Product Introduction

  6. Thanks! intelligent software, pleasant work www.vayoinfo.com

More Related