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XILINX CPLDs The Total ISP Solution

XILINX CPLDs The Total ISP Solution. XC9500/XL CPLDs Provides Total Solution Built for ISP & Superior Pin-Locking Uses Advanced Flash Technology Complete ISP/ATE Software Support. Building CPLDs For Total Product Life Cycle Support. Field Upgrades. Product Life Cycle. Proto- typing.

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XILINX CPLDs The Total ISP Solution

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  1. XILINX CPLDsThe Total ISP Solution

  2. XC9500/XL CPLDs Provides Total Solution Built for ISP & Superior Pin-Locking Uses Advanced Flash Technology Complete ISP/ATE Software Support Building CPLDs For TotalProduct Life Cycle Support Field Upgrades Product Life Cycle Proto- typing Manufacturing & Test

  3. XC9500 Delivers Better ISP Solution Industry’s Best ISP with Pin-Locking • Rapid prototyping and design fix implementation • Streamlined manufacturing flows • Flexibility to handle reprogramming during field upgrades 1. Reduced Time To Market Customer Benefits 2. Reduced Costs 3. Reduced Risk

  4. XC9500/XL CPLDs Key Features • Flexible ISP architecture with superior pin-locking • XC9500: 5v family • XC9500XL: 3.3v family • High performance: 4ns pin-to-pin (XL) • Full IEEE 1149.1 JTAG • 5v/3.3v/2.5v I/O compatibility • Highest reprogramming reliability • Space-efficient packaging • Low cost

  5. Xilinx CPLD Process Leadership Non-Volatile Year used in Year used in SPLD/CPLD Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI 5V FLASH 1990 1995 Xilinx XC9500 3.3V FLASH 1993 1998 Xilinx XC9500XL

  6. FLASH Technology EnablesRapid Die Size Reduction

  7. CPLD Price Leadership • Without Compromises • Flexible ISP • tPD = 4ns (‘99); 2.5ns (‘02) • Best Pin-Locking • Industry Standard JTAG • 2.5V (0.25u Flash) in 1999 $20 288 Macrocells $9 $ (unit price) $5.75 144 Macrocells $3.95 $1.20 36 Macrocells $0.80 * Prices are based on 100Ku+, slowest speed grade, lowest cost package

  8. 3X improvement in 5 years Leadership Performance CPLDs fSYS (MHz) 300 300 0.18µ 250 250 0.25µ 200 200 0.35µ 150 100 0.6µ/0.5µ 100 50 Year 1996 1997 1998 1999 2000 2001/2

  9. Low Power CPLDs 5v Core Voltage 1.0 .75 Power (normalized) 3.3v .5 2.5v .25 1.8v 1995 1996 1997 1998 1999 2000 2002 Year * Same frequency and typical utilization

  10. Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Uses standard IR techniques for mounting to PC board

  11. New XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL 288 Macrocells 36 72 144 6400 Usable Gates 800 1600 3200 tPD (ns) 4 5 5 6 200 178 178 151 fSYSTEM Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 352BG (192) BGA CSP

  12. XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 44VQ (34) 48 CSP(34) 44PC (34) 44PC (34) 84PC (64) 100TQ (72) 100PQ (72) 84PC (69) 100TQ (81) 100PQ (81) 160PQ (108) 100TQ (81) 100PQ (81) 160PQ (133) 208HQ (168) 352BG (192) 160PQ (133) 208HQ (166) 352BG (166)) XC9500 5V Family Macrocells 36 72 108 144 216 288 Usable Gates 4800 800 1600 2400 3200 6400 tPD (ns) 10 5 7.5 7.5 7.5 15 fSYSTEM 100 83 83 83 56 67 Max. User I/Os 34 72 108 133 192 166 Packages (Max. User I/Os)

  13. Productive Implementation Flow for CPLDs • Simplified Project Management • Implementation Templates for Speed & Density • Push Button Design Flows USER BENEFITS • Faster Clock Speeds • Higher Device Utilization • optimized logic/cm2 • Industry’s Best Pin-Locking • more design flexibility, less risk, lower cost

  14. What’s New In V1.5CPLDs • Evolutionary Logic Algorithms for XC9500 5V CPLDs • higher clock frequencies, improved density & faster runtimes • Full Support of XC9500XL 3.3V CPLDs • Includes “Advance” speed grades for fastest XC9500XL devices • Improved Timing Driven CPLD Fitting • JTAG Programmer now supports: • XC9500/XL CPLDs, Virtex, XC4000E/X/XL, XC5200, SPARTAN/XL FPGAs • XC9500/9500XL support in LogiBLOX • AllianceCORE CPLD based IP

  15. XILINX CPLDsThe total ISP solution • Complete support of customer’s Product Life Cycle • Industry’s best pin-locking CPLD at lowest price • Multiple software solutions to choose from • Based on leadership FLASH technology

  16. CPLD Roadmap Appendix

  17. CPLD Product Roadmap Advanced Architecture 0.18µ/6LM/1.8V K2 0.25µ/5LM/2.5V XC9500XV 0.35µ/4LM/3.3V XC9500XL Long Term Availability 0.5µ/3LM/5V* XC9500 0.6µ/2LM/5V XC9500 1996 1997 1998 1999 2000 2001 2002 * 0.5µ transistor with 0.35µ interconnect

  18. CPLD Family Overview Fastest Speed Family Process Voltage tPD fSYS I/Os XC9500 5V 5ns 100 MHz Mixed system* capability 0.6µ XC9500 5V 5ns 125 MHz Mixed system* capability 0.5µ/0.35µ XC9500XL 3.3V 4ns 200 MHz 5 volt compatible** I/Os 0.35µ XC9500XVA 2.5V 225+ MHz 3.3 volt I/O, 5 volt compatible** 0.25µ <4ns *Can safely drive 3 volt devices when in “TTL mode” **Can be safely driven with 5 volt logic and can drive TTL levels

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