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Memory segmentation and addressing

Memory segmentation and addressing. Von – Newman architecture & Harvard architecture Program Memory & Data Memory Need for Segmentation To implement Harvard architecture Easy to debug Same Interfacing ICs can be used To avoid overlap of stack with normal memory Compatible with 8085.

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Memory segmentation and addressing

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  1. Memory segmentation and addressing • Von – Newman architecture & Harvard architecture • Program Memory & Data Memory • Need for Segmentation • To implement Harvard architecture • Easy to debug • Same Interfacing ICs can be used • To avoid overlap of stack with normal memory • Compatible with 8085

  2. Segmented Memory

  3. Offset Value (16 bits) 0 0 0 0 Segment Register (16 bits) Adder Physical Address (20 Bits) Memory Address Generation • The BIU has a dedicated adder for determining physical memory addresses.

  4. Segment : Offset Address • Logical Address is specified as segment:offset • Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address. • Thus the physical address of the logical address A4FB:4872 is: A4FB0 + 4872 A9822

  5. Segments, Segment Registers & Offset Registers • Segment Size = 64KB • Maximum number of segments possible = 14 • Logical Address – 16 bits • Physical Address – 20 bits • 2 Logical Addresses for each Segments. • Base Address (16 bits) • Offset Address (16 bits) • Segment registers are used to store the Base address of the segment.

  6. Segments, Segment Registers & Offset Registers • 4 Segments in 8086 • Code Segment (CS) • Data Segment (DS) • Stack Segment (SS) • Extra Segment (ES)

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