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2001 ITRS Overall Roadmap Technology Characteristics (ORTC)

2001 ITRS Overall Roadmap Technology Characteristics (ORTC). A.Allan / P.Gargini 2001 ITRS Roll-out Intel Santa Clara 11/29 Rev 2a, 11/29/01. Agenda. New Technology Nodes Technology Node Timing MPU Frequency (Example) Summary. S=0.7 [0.5x per 2 nodes]. Pitch. Gate.

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2001 ITRS Overall Roadmap Technology Characteristics (ORTC)

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  1. 2001 ITRS Overall Roadmap Technology Characteristics (ORTC) A.Allan / P.Gargini 2001 ITRS Roll-out Intel Santa Clara 11/29 Rev 2a, 11/29/01

  2. Agenda • New Technology Nodes • Technology Node Timing • MPU Frequency (Example) • Summary

  3. S=0.7 [0.5x per 2 nodes] Pitch Gate MOS Transistor Scaling(1974 to present) Source: 2001 ITRS - Exec. Summary, ORTC Figure

  4. Poly • Pitch • Metal • Pitch (Typical MPU/ASIC) (Typical DRAM) Half Pitch (= Pitch/2) Definition Source: 2001 ITRS - Exec. Summary, ORTC Figure

  5. Technology Nodes (nm) Actual % WAS X IS 100 X 130 0.7 91 90 -10.00 X 70 90 0.7 64 65 -7.14 X 50 65 0.7 45 45 -10.00 X 35 45 0.7 31 32 -8.57 X 25 32 0.7 22 22 -12.00 Back to Basics

  6. 1994 NTRS - .7x/3yrs Log Half-Pitch Actual - .7x/2yrs 0.7x 0.7x Linear Time 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% N N+1 N+2 * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Scaling Calculator + Node Cycle Time: Source: 2001 ITRS - Exec. Summary, ORTC Figure

  7. 2001 ITRSTiming Highlights • The DRAM Half-Pitch (HP) remains on a 3-year-cycle trend after 130nm/2001 • The MPU/ASIC HP remains on a 2-year-cycle trend until 90nm/2004, and then remains equal to DRAM HP (3-year cycle) • The MPU Printed Gate Length (Pr GL ) and Physical Gate Length (Ph GL) will be on a 2-year-cycle until 45nm and 32nm, respectively, until the year 2005 • The MPU Pr GL and Ph GL will proceed parallel to the DRAM/MPU HP trends on a 3-year cycle beyond the year 2005 • The ASIC/Low Power Pr/Ph GL is delayed 2 years behind MPU Pr/Ph GL • ASIC HP equal to MPU HP

  8. 200 K 100 M Development Production 20 K 10 M 2 K 1 M Beta Alpha Production Volume (Wafer/Month) Tool Tool Tool Volume (Parts/Month) 100 200 K First two 20 10 K companies First reaching 2 1 K Conf. production Papers 0 12 24 -12 -24 Months Production Ramp-up Model and Technology Node Source: 2001 ITRS - Exec. Summary, Figure

  9. Source: 2001 ITRS - Exec. Summary, ORTC Figure

  10. 2001 ITRS ORTC Node Tables Source: 2001 ITRS - Exec. Summary, ORTC Table

  11. [3-Year Node Cycle] [Node = DRAM Half-Pitch (HP)] [MPU Gate Length Cycle (GL)]: [2-year cycle] [3-year cycle] [MPU HP/GL Cycle]: [3-year cycle] 2001 ITRS ORTC Node Tables – w/Node Cycles

  12. Source: 2001 ITRS - Exec. Summary, ORTC Figure

  13. Table 4c Performance and Package Ch ips: Frequency On - Chip Wiring Levels — Near - Term Years 2001 2002 2003 2004 2005 2006 2007 Y P EAR OF RODUCTION 130 115 100 90 80 70 65 DRAM ½ Pitch (nm) 150 130 107 90 80 70 65 MPU/ASIC ½ Pitch (nm) 90 75 65 53 45 40 35 MPU Printed Gate Length (nm) Chip Frequency (MHz) 65 53 45 37 32 28 25 MPU Physical Gate Length (nm) 1,684 2,317 3,088 3,990 5,173 5,631 6,739 On - chip local clock Chip - to - board (off - chip) speed 1,684 2,317 3,088 3,990 5,173 5,631 6,739 (high - performance, for peripheral buses)[1] 7 8 8 8 9 9 9 Max imum number wiring levels — maximum 7 7 8 8 Maximum number wiring levels — minimum 8 9 9 Table 4d Performance and Package Chips: Frequency, On - Chip Wiring Levels — Long - term Years 2010 2013 2016 Y P EAR OF RODUCTION 45 32 22 DRAM ½ Pitch ( nm) 45 32 22 MPU/ASIC ½ Pitch (nm) 25 18 13 MPU Printed Gate Length (nm) 18 13 9 MPU Physical Gate Length (nm) Chip Frequency (MHz) 11,511 19,348 28,751 On - chip local clock Chip - to - board (off - chip) speed 11,511 19,348 28,751 (high - performance, for peripheral buses)[1] 10 10 10 Maximum number wiring levels — maximum 9 9 10 Maximum number wiring levels — minimum 2001 ITRS ORTC MPU Frequency Tables Source: 2001 ITRS - Exec. Summary, ORTC Table

  14. Table 4c Performance and Package Ch ips: Frequency On - Chip Wiring Levels — Near - Term Years 2001 2002 2003 2004 2005 2006 2007 Y P EAR OF RODUCTION 130 115 100 90 80 70 65 DRAM ½ Pitch (nm) 150 130 107 90 80 70 65 MPU/ASIC ½ Pitch (nm) 90 75 65 53 45 40 35 MPU Printed Gate Length (nm) Chip Frequency (MHz) 65 53 45 37 32 28 25 MPU Physical Gate Length (nm) 1,684 2,317 3,088 3,990 5,173 5,631 6,739 On - chip local clock Chip - to - board (off - chip) speed 1,684 2,317 3,088 3,990 5,173 5,631 6,739 (high - performance, for peripheral buses)[1] 7 8 8 8 9 9 9 Max imum number wiring levels — maximum 7 7 8 8 Maximum number wiring levels — minimum 8 9 9 [2-Yr GL Cycle; then 3-Yr] Table 4d Performance and Package Chips: Frequency, On - Chip Wiring Levels — Long - term Years 2010 2013 2016 Y P EAR OF RODUCTION 45 32 22 DRAM ½ Pitch ( nm) 45 32 22 MPU/ASIC ½ Pitch (nm) 25 18 13 MPU Printed Gate Length (nm) 18 13 9 MPU Physical Gate Length (nm) Chip Frequency (MHz) 11,511 19,348 28,751 On - chip local clock Chip - to - board (off - chip) speed 11,511 19,348 28,751 (high - performance, for peripheral buses)[1] 10 10 10 Maximum number wiring levels — maximum [3-year cycle] 9 9 10 Maximum number wiring levels — minimum 2001 ITRS ORTC MPU Frequency Tables – w/Node Cycles

  15. 2001 ITRS (3-year Node Cycle) Design TWG MPU Frequency: ~2x/3yrs from 2001-2010; then ~2x/5yrs from 2010-2016 Scenario w/Innovatio: 2x/2yrs Non-Gate-Length Performance Innovation 1999 ITRS trend 9.6Ghz/11nm 25Ghz/4.2nm 20Ghz/5.5nm 4.8Ghz/22nm 2.4Ghz/45nm 1.2Ghz/90nm 3.4Ghz/32nm .6 Ghz/180nm 1.7Ghz/65nm 2011 2023 .3 Ghz/350nm 2001 2005 Scenario (w/o Innovation): 1999-2005 Freq = 2x/4yrs ; GL = .71x/2yr 2005- 2016 Freq = 2x/6yrs ; GL = .71x/3yr Historical: Freq = 2x/2yrs ; GL = .71x/yr 1995 1999 1997 2003 2008 2014 Log Frequency 2010 2016 2013 MPU Max Chip Frequency – 2001 ITRS Design TWG Model vs 1999 ITRS, and 2000 Update Scenario “w/o Innovation”

  16. Summary • New Technology Nodes defined • Technology acceleration (2-year cycle) continues in 2001 ITRS • Gate length reduction proceeding faster than pitch reduction (until 2005) • DRAM half-pitch is expected to return to a 3-year cycle after 2001 but….so we have said before • DRAM and MPU half-pitch dimensions will merge in 2004 • Innovation will be necessary, in addition to technology acceleration, to maintain historical performance trends

  17. Words to the Wise… • “Word.. without Action.. is Dead” – James ca 1st Century • “Simplest..is Best” – William of Ockham, ca 13th Century • “Better..Faster..Cheaper” – Craig Barrett, ca 21st Century (and also daily) • “Talk..is Cheap” – Semiconductor Suppliers

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