How Computers Work Lecture 6 Finite State Machines

1. How Computers WorkLecture 6Finite State Machines

2. PC Q XADDR RA1 Memory RD1 JMP(R31,XADDR,XP) ISEL 0 1 31:26 25:21 20:5 9:5 4:0 OPCODE RA C RB RC +1 0 1 OPCODE Register File RA1 RD1 Register File RA2 RD2 SEXT ASEL BSEL 0 1 2 1 0 A ALU B ALUFN A op B Z RA2 Memory RD2 PCSEL 0 1 0 1 2 WDSEL D PC WD Memory WA WD Register File WA RC WE WEMEM WE WERF One FSM: The Beta

3. A generic form of exemplified by the Beta:The (Synchronous) Finite State Machine (FSM) IN OUT Logic (describable by truth table) NEXT STATE CURRENT STATE Memory CLOCK

4. Another FSM: A (Primitive) Coke Machine • 1. Coke Costs $0.15 • 2. Only Nickels + Dimes Accepted • 3. FSM Inputs: • 5: Nickel • 10: Dime • Coke: Give-me-a-coke • Return: Give-me-my-money-back • 4. FSM Outputs: • Drop-a-coke (Drop) • Return $.05 (Ret5) • Return $.10 (Ret10) • Return $.15 (Ret15) COKE

5. State Diagramfor a primitive Coke Machine

6. Rules for DesigningFSM State Diagrams • Arcs out of a state must be mutually exclusive • Arcs out of a state must be exhaustive (use * to make this job easier) • The starting state should be defined • All possible states should be defined, with transitions to starting state • S states requires 2 ^ S state variables

7. The Synchronous FSM IN OUT Comb. Logic NEXT STATE CURRENT STATE Synch. Delay CLOCK

8. MEALY MOORE in out in out current state next state current state next state Q D Q D clk clk i21 i21,o21 s1 s2 s1,o1 s2,o2 i11,o11 i22,o22 i11 i22 i12 i12,o12 Mealy vs. Moore

9. Mealy vs. Moorefrom a Truth Table CURRENT NEXT STATE IN STATE OUT 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 ... ... This is a Mealy machine

10. Next State C.L. Output C.L. in out in out D Q current state next state clk current state Q D clk Another Way of DrawingMoore FSMs

11. Why do we need the synchronizing element? IN OUT Logic STATE

12. A Human ExperimentMake a power-of-2 sequence generator from 2 adders:

13. Experiment 1 • Wait your turn • Immediately Look at the two numbers on the board • Immediately Erase the number in front of you • Immediately Add them in your head • Immediately Write the result in front of you • Walk away • Experiment 2 • Follow the instructions of your sergeant / lecturer

14. in out C.L. clk current state next state Q (current state) Q D D (next state) clk PossibleSynchronizing Elements • The Register, a.k.a. the Edge Triggered Flip-Flop

15. Edge-Triggered F-F Input Timing D CLK Th = Hold Time Ts = Setup Time

16. in out G C.L. current state next state Q (current state) Q D D (next state) G clk PossibleSynchronizing Elements • The Transparent Latch

17. 0 Q D 1 G MUX Implementation of the Transparent Latch D G Q

18. Input Specifications for the Transparent Latch D G Th = Hold Time Ts = Setup Time

19. The Globally Synchronous Discipline • NO LOGIC CYCLES - All Cycles Are Broken by at least 1 Synchronizing Delay • All Synchronizer Inputs obey timing requirements ( Tsetup, Thold )

20. 1 2 3 4 5 6 Timing Constraints • Transparent Latch G in out Logic current state current state next state next state Q D G Tpd minG-Q < t13 Tpd maxG-Q > t14 Tpd min Logic < t35 Tpd max Logic > t46 clk t12 < Tpd min G-Q + Tpd min Logic - Thold

21. Edge Triggered Flip-Flop 1 clk in out 3 4 C.L. current state current state next state 5 6 next state Q D clk Thold < Tpd minC-Q + Tpd minC.L. Timing Constraints Tpd minG-Q < t13 Tpd maxG-Q > t14 Tpd min Logic < t35 Tpd max Logic > t46

22. clk in out C.L. current state current state next state next state Q D clk Clock Period > ___________ Maximum Frequency T pd max c-q + T pd max cl + T setup

23. C.L. Skew D Q D Q clk1 clk2 T cd c-q + T cd cl - T hold Tskew < _______________________________

24. A Few Details • What Happens if the Logic has Glitchy Outputs? in out current state next state Q D clk

25. in out D Q current state next state clk Q D clk De-Glitching FSM Outputs • Assumption: Registers Glitch Free if output doesn’t change from cycle to cycle. • Consequence: Output Delayed

26. Summary • Today’s Lecture • Every modern computer is a finite state machine • There is a straightforward art to designing FSMs • Timing is important, but there is a discipline for insuring correct operation. • Recitation • Practical Practice designing and implementing FSMs