Embedded Fault Diagnosis for Digital Logic Exploiting Regularity

1. Embedded Fault Diagnosis for Digital Logic Exploiting Regularity R. Kothe, H. T. Vierhaus Brandenburg University of Technology Cottbus Computer Science Department Computer Engineering Group

2. Outline • Introduction: Fault Diagnosis - when and what for? • Scan Test and Pattern Compaction • How Fault Diagnosis is Done • Embedded Fault Diagnosis Based on Regularity • Summary and Conclusions

3. 1. Introduction Fault diagnosis becomes a must for production test of ICs and for self-test „in the field“.

4. Test-Technology-Traditionally Production test In-field test Prototype test Time hours to days seconds to minutes seconds to minutes Cost 1000-10000$ cents to a few $ (none) Quantity 5 to 100 thousands to millions (individual test) Destructiveoften never never Diagnosisyes hardly little

5. Test Technology for Nano-Technologies In-field test Prototype test Production test Time hours to days seconds to minutes seconds to minutes cost 1000-10000$ cents to a few $ (none) quantity 5 to 100 thousands to millions (individual test) Destructiveoften never never Diagnosisyes yes, must be yes, must be for repair for yield optimization for self-repair

6. New Problems with Nano-Technologies Light source Wave length: 193 nm mask (reticle) resist exposed resist wafer Feature size: down to 45 nm

7. Layout Correction Modified layout for compensation of mapping faults Compensation is critical and non-ideal Faults are not random but correlated ! Requires fast fault diagnosis

8. Built-in Self Repair (BISR) backup / replacement blocks Logic test must identify the faulty block before repair / replacement ! r f Problem: There is no powerful test machine available ! Logic blocks

9. Why Diagnostic Test is Needed Traditional IC production test does not care for fault diagnosis. Fabrication in nanometer technologies uses exposure wavelengths that are up to5 times longer than the minimum feature size. All layout features need an „advanced“ correction to compensate for mapping faults. This correction is non-ideal. Diagnostic test is required to find faulty layout corrections for fast „ramp up“ in production yield. Built- in Self Repair (BISR) for long-time dependable systems requires „built-in“ diagnostic test as a pre-condition!

10. Basic Questions Can diagnosis be done on top-of production test technology with massive test data compression ? How good can the diagnostic resolution be ? Is a fine – grain diagnosis as a pre-condition for built- in self repair possible „in the field“ at reasonable cost / overhead ? Can production test technology be compatible with in-field testing ? Note:All answers are „yes“ for regular structures such as memory blocks !

11. 2. Scan Test and Pattern Compaction The workhorse of test technology has to do a variety of jobs never thought of by the it inventors.

12. Scan-Based IC Test

13. Essentials of Scan Testing Multiple scan paths (100 to 1000). Scan path allocation / partitioning without making any use of logic regularity. No whatsoever usage of functional features. Test sets are strictly minimized, no specific patterns for fault diagnosis. Fault diagnosis has to come combined with or „on top“ of compaction mechanisms. Identical problems for compaction / diagnosis for external test or built-in self test (logic BIST).

14. Multi-Scan Path IC Test Pattern Memory Test External Tester Processor control (optional for „embedded“ scan test) encoded test patterns Pattern Generator ) (LFSR Multiple parallel scan paths MISR Compacted test response

15. Data Compression / Compaction On-line Pattern Memory C O M P ATPG Test External Tester Processor control encoded test Off-line patterns Pattern Generator Compaction rate: 50-500 ) (LFSR Multiple parallel scan paths Space Compactor (XOR-tree) Compaction rate: 100-1000 Time comp. (MISR)

16. Advanced Scan Test Requirements Fast scan-test for production test without fault diagnosis. Fast scan test for production with additional (off-line) fault diagnosis. Scan output analysis with detailed on-chip diagnosis for „silicon debug“. Scan output analysis with high-resolution diagnosis as a pre-process for logic self repair. Diagnosis may be done: In parallel with fault detection Encoding / parity bits? Selectively after fault detection MISR-based compaction and analysis?

17. 3. How Fault Diagnosis is Done Fault Diagnosis has to be combined with test output compaction / compression. Compaction can be done in space and in time, but loss of diagnostic information is a problem.

18. Space-Compaction and Fault Masking (pseudo - ) (pseudo - ) Fault is „absorbed“ inputs outputs Output vector f fault + + Comb. + out Logic f + Input vector + Remedy: Avoid multiple output paths by ATPG!

19. Fault Detection by Direct Comparison (pseudo - ) (pseudo - ) outputs inputs Input Comb. vector Scan C path logic ordered by O fault „good“ response M P A clock R Test Processor E „Good“ outputs Ref - out Compare ordered, number of upon appearances noted detected fault Ref - Pattern

20. Error Detection Using Compressed Outputs

21. MISR-Based Compaction in Time A multi-input signature register (MISR) can do a compaction „in time“. FF FF FF FF + + + + In case of multiple fault events, fault masking is also possible due to „aliasing errors“.

22. Diagnosis by Variable MISR Allocation

23. Coding-Based Diagnosis Scan Input Generator (De - Compactor ) scan clock Code-word d d d d d d d 0 1 2 3 4 5 6 storage & & & & & & & Application of multiple code-words to the same scan output MISR Backup MISR Read-out for external analysis

24. Top Compaction & Diagnosis Technologists • Janusz Rajski (Mentor Graphics, formerly PUT) and Jerzy Tyszer ( PUT) • Michael Gössel, Jan Rzeha (Univ. of Potsdam) • Ralf Pöhl, Andreas Leininger (Infineon Technologies, Munich)

25. Coding-Based Diagnosis Patented by Infineon Technologies AG and U. Potsdam, 2004

26. How the Scheme Works In the „normal“ test mode, all d-inputs are set to „1“. The MISR will indicate that a fault has occurred after compaction of one or more full test responses. In the diagnosis mode, the test for the faulty vector is re-applied again. Then the output is encoded in k steps with k being the number needed to implement a fault detecting code for the n scan path outputs. For collecting the diagnosis output, the MISR is operated as a shift register without feedback. The d-inputs are set according to the rules of the code. After k cycles of a local MISR clock, the diagnosis information is stored in the MISR / shift register. Using a Hamming code, an XOR-comparison between the actual output and a reference output directly reveals the faulty scan chain.

27. d0 d1 d2 d3 d4 d5 d6 d7 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 Coding Error det. codes , 1 1 0 1 1 0 1 1 width depending on the number 1 0 1 0 1 1 0 1 of scan chains and the diagnostic 1 1 0 1 0 1 0 0 resolution ! Error coding is the same Test - Output ! for every test pattern & Analysis MISR ( error code ) The result can also accommodate multiple faults ! Output Encoding

28. Features and Limitations Multiple faults can be diagnosed, depending on the code applied. In case of Hamming code, faults that are related to a diagonal in the d-matrix cannot be resolved. The set of d-bits used for encoding is independent of the test output. It can be stored locally and is applied repeatedly. The reference pattern for detection of the „faulty“ output bit needs to be supplied for every bit output vector. In this version, the scheme cannot yet handle „undetermined“ scan outputs.

29. The „X Output Problem“ Test responses in scan test may include „undetermined“ output values. Most compaction schemes cannot handle „X“-bits, but need to replace them by deterministic settings. The information „which output bit on which scan chain“ needs to be set, can be as large as the (compressed) input pattern file itself !

30. Encoding Test Outputs Scan Input Generator (De - Compactor ) scan clock Multiple parallel scan paths X-blanking information Code- bits Encoder / Compactor Signature

31. 4. „Embedded“ Fault Diagnosis Built-in self repair needs to be done „in the field“ with limited resources for test and diagnosis.

32. Built-in Fault Diagnosis? Pattern- ROM Scan Input Generator (De - Compactor ) Test Processor scan clock 16 RAM d d d d d d d d - value 0 1 2 3 4 5 6 storage & & & & & & & MISR clock : MISR k * scan - clock a Stop / activate MISR feedback compare Ref. MISR Ser. / parallel load

33. No Solution for „Embedded“ Diagnosis? For efficient diagnosis by as-few- as- possible parity bits, long registers / MISRs are required (100-1000 bits!) A reference MISR is needed in order to detect the clock cycle at which a specific scan path had a fault. The diagnosis reference patterns must either be stored and supplied (e.g. one for every test pattern). A workable solution for a few specific tests, but not in the general case!

34. Regularity in Logic Designs Scan paths and MISR sections are associated with „equal“ structural entities.

35. Regularity in Test Generation Equal sections can be fed in parallel with the same test patterns. control LFSR scan- path M1 1 M1 2 M2 1 M2 2 M3 1 M3 2 M3 3 Simplified ATPG, smaller and faster pattern input compaction circuitry!

36. Fault Diagnosis by „Virtual Majority Vote“

37. Registration of Fault Events

38. Single / Double Fault Events Unit 1 2 3 4 5 6 7 8 Unit 1 2 3 4 5 6 7 8 1 1 + + + + + + + + + + + + + + + + single fault double fault Unit 1 2 3 4 5 6 7 8 Unit 1 2 3 4 5 6 7 8 1 1 + + + + + + + + + + + + + + + + double fault double fault

39. Triple Fault Events Unit 1 2 3 4 5 6 7 8 Unit 1 2 3 4 5 6 7 8 1 1 + + + + + + + + + + + + + + + + triple fault triple fault Unit 1 2 3 4 5 6 7 8 Unit 1 2 3 4 5 6 7 8 1 1 + + + + + + + + + + + + + + + + double single triple fault triple fault

40. Usage for Built-in Self Repair? Designs that facilitate built-in self repair will be composed from a limited number of different functional units (NAND, NOR, FF) have „internal“ redundancy. Logic will become regular!

41. Signal Processing Architecture c c Addierer Addierer 0 0 Input Input Output Output x x + + + + y (n) y (n) x (n) x (n) Multipliz Multipliz . . d d 1 1 Z Z Z Z - - 1 1 - - 1 1 c c 1 1 x(n x(n - - 1) 1) x x x x y (n y (n - - 1) 1) + + + + Verzöge Verzöge - - rungen rungen Z Z d d Z Z - - 1 1 - - 1 1 c c 2 2 2 2 x x x x y (n y (n - - 2) 2) + + + + x(n x(n - - 2) 2) c c Z Z - - 1 1 Z Z d d - - 1 1 3 3 3 3 x x x x + + + + x(n x(n - - 3) 3) y (n y (n - - 3) 3) c c d d M M - - 1 1 N N - - 1 1 y (n y (n - - N N - - 1) 1) x(n x(n - - M M - - 1) 1) x x + + x x + + Z Z Z Z - - 1 1 - - 1 1 c c d d M M N N x x x x + + + + x(n x(n - - M) M) y(n y(n - - N) N) ... are typically regular by nature!

42. 5. Summary and Conclusions Fault diagnosis becomes an indispensable part of test. Fault diagnosis for highly irregular logic structures becomes expensive. DSP architectures and re-configurable logic architectures are inherently regular. Exploiting regularity for test generation and for fault diagnosis can reduce the need for reference outputs significantly, facilitating embedded fault diagnosis. Strongly correlated faults need reference data!

43. What Else?? There is still a lot of work to do before we will have highly dependent nano-electronic circuits and systems. Thank You for Your Attention!!