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Readout and DAQ for Micromegas

Readout and DAQ for Micromegas. Guillaume Vouters. Plan. The HCAL Architecture ASUs developed at LAPP for MICROMEGAS ASU 8x32 with HARDROC v.1 ASU 32x48 with HARDROC v.2 for m² ASU 8x8 with DIRAC v.1/DIRAC v.2 DIF developments Firmware for ASICs Firmware for the CALICE DAQ.

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Readout and DAQ for Micromegas

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  1. Readout and DAQ for Micromegas Guillaume Vouters

  2. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  3. The HCAL Architecture • One cubic meter technological prototype : •  40 plans • 400 000 channels • “Digital” Readout : 3 thresholds • Power pulsing Readout and DAQ for Micromegas -- Guillaume Vouters

  4. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  5. ASU 8x32 with HARDROC v.1 • First we tried to communicate with our boards • We managed to control 12 HARDROCs v.1 Readout and DAQ for Micromegas -- Guillaume Vouters

  6. ASU 8x32 with HARDROC v.1 • Then we built bulk MICROMEGAS • We have now 4 detectors but there are only 11 HARDROCs v.1 still working Readout and DAQ for Micromegas -- Guillaume Vouters

  7. ASU 8x32 with HARDROC v.1 Readout and DAQ for Micromegas -- Guillaume Vouters

  8. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  9. Architecture of the m² Intermediate board Samtec connection DIF Intermediate board Samtec connection DIF Intermediate board DIF Samtec connection : Flat Printed Circuit : ASIC chip (64 channels) : Hirose connector : Terminasion component Readout and DAQ for Micromegas -- Guillaume Vouters

  10. ASU 32x48 with HARDROC v.2 • Here is a part of the square meter • We managed to control 48 HARDROCs v.2 Readout and DAQ for Micromegas -- Guillaume Vouters

  11. MICROMEGAS m² ~1 m 2 type of ASU PCB Intermediate board 32x48 cm ( 24 ASICs ) (HARDROC or DIRAC) 32x48 cm ( 24 ASICs ) (HARDROC or DIRAC) Samtec connection DIF Intermediate board 32x48 cm ( 24 ASICs ) (HARDROC or DIRAC) 32x48 cm ( 24 ASICs ) (HARDROC or DIRAC) Samtec connection DIF Type 1 ~1 m 32x48 cm ( 24 ASICs ) (HARDROC or DIRAC) 32x48 cm ( 24 ASICs ) (HARDROC or DIRAC) Intermediate board DIF Samtec connection Type 2 (with terminasion) Readout and DAQ for Micromegas -- Guillaume Vouters

  12. Test Box for ASU 32x48 Readout and DAQ for Micromegas -- Guillaume Vouters

  13. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  14. ASU 8x8 with DIRAC v.1 • Dirac was initially developed at IPNL but now in tight collaboration with LAPP • First digital ASIC embedded on a bulk MICROMEGAS: tested successfully in 2008 beam test Readout and DAQ for Micromegas -- Guillaume Vouters

  15. ASU 8x8 with DIRAC v.2 Setup for DIRAC v.2 ASU DIRAC v.2 wasfullycharactarizedat LAPP Readout and DAQ for Micromegas -- Guillaume Vouters

  16. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  17. Detector InterFace developments The DIF boardis the first intermediateboardbetweenASUs and DAQ This DIF (see picture) has been developed at LAPP and has already been used in 2008 and 2009 for Eu-DHCAL MICROMEGAS and RPC beamtests This DIF isalso compatible with ECAL and AHCAL detectors Readout and DAQ for Micromegas -- Guillaume Vouters

  18. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  19. Detector InterFace developments Firmwarealreadyexisting for : HARDROCs 1 used by LAPP (MICROMEGAS) and IPNL (RPC) HARDROCs 2 used by LAPP (MICROMEGAS) and soon IPNL (RPC) DIRAC 2 used by LAPP (MICROMEGAS) Readout and DAQ for Micromegas -- Guillaume Vouters

  20. Plan • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASICs • Firmware for the CALICE DAQ • The HCAL Architecture • ASUs developed at LAPP for MICROMEGAS • ASU 8x32 with HARDROC v.1 • ASU 32x48 with HARDROC v.2 for m² • ASU 8x8 with DIRAC v.1/DIRAC v.2 • DIF developments • Firmware for ASIC • Firmware for the CALICE DAQ Readout and DAQ for Micromegas -- Guillaume Vouters

  21. Detector InterFace developements Firmware is on going for the CALICE DAQ LAPP participates in the DIF Task Force which elaborates the CALICE DAQ protocol Purpose: Perform a cubic meter with 400 000 channels read by DIFs and store data on a PC through the DAQ. Readout and DAQ for Micromegas -- Guillaume Vouters

  22. Conclusion Developments of DHCAL readout and DAQ is in a good way :  DIF boards and VHDL firmware for different ASICs  Tests of various readout chips (Hardroc, Dirac) Dirac optimized for MICROMEGAS  Work on a future CALICE DAQ Should be ready in 2011 Readout and DAQ for Micromegas -- Guillaume Vouters

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