1 / 15

FPGA-BASED LOW LEVEL CONTROL OF CERN’S LINAC 3 CAVITIES

FPGA-BASED LOW LEVEL CONTROL OF CERN’S LINAC 3 CAVITIES. Javier Serrano CERN, Geneva, Switzerland. Summary. Context The problem Traditional analog solutions The LRFSC card Control system design Implementation and results. Ions in the LHC. The problem.

dylan-potter
Download Presentation

FPGA-BASED LOW LEVEL CONTROL OF CERN’S LINAC 3 CAVITIES

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. FPGA-BASED LOW LEVEL CONTROL OF CERN’S LINAC 3 CAVITIES Javier Serrano CERN, Geneva, Switzerland

  2. Summary • Context • The problem • Traditional analog solutions • The LRFSC card • Control system design • Implementation and results

  3. Ions in the LHC

  4. The problem • The amplitude A and phase φof the RF electric field in a cavity are subject to external perturbations (50 Hz power, temperature, the beam…). • A feedback system is needed to control it, i.e. measure it, compare it and adjust it. φ x(t) = A cos(ωt - φ) or x(t) = I cos(ωt) + Q sin(ωt) with I = A cos(φ) Q = A sin(φ) A A Q φ ωt I

  5. Overview of feedback system CAVITY Solid state amplifier Controller Forward Pickup Reflected Cavity Q Set Points from Control Room I

  6. Analog demodulation Phase detector has limited range and exhibits AM to PM coupling. x(t) Low pass filter A φ X Low pass filter LO (Local Oscillator) I Low pass filter 0º Both paths must be identical: perfect splitter, perfect 90º, etc. x(t) X LO 90º X Q Low pass filter

  7. Digital IQ demodulation x(t) xd(t) xs(t) Low pass filter ADC FPGA X LO (Local Oscillator) clk One single analog path FPGA implements multiplication by sine and cosine tables and digital low pass filtering. If clk’s frequency is exactly four times that of xd(t): I xs(t) De-mux +/-1 LPF Q +/-1 LPF

  8. LRFSC card block diagram

  9. The LRFSC card

  10. Control system design: the cavity model Transfer functions: RF I and Q

  11. Control system design: methodology • Plot frequency response of open loop system (PI controller followed by cavity). • Set KI/KP = s so that the controller zero cancels the cavity pole. This gives us one equation. • The other equation needed comes from the requirement that the cabling delay should represent 45° at the frequency where the open loop gain is 1. This gives a total phase margin of 45°, ensuring global stability.

  12. Control system design: implementation • Digital PI using rectangular rule for integration. • 28 bit integrator with anti-windup. • Saturation preferred to scaling throughout except in IQ Modulator. • Data paths vary between 14 and 41 bits inside the design. Tradeoff between speed and accuracy.

  13. HW/SW interaction 400 ms 200 ms RF ON VME Interrupt PowerPC VME master writes control information and reads back diagnostics

  14. Results Theory Experiment

  15. Thanks!

More Related