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EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems. Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu. Digital Design with VHDL. Lecture 15. Resolved Signals. A resolution function is used to compute a value for a signal based on multiple drivers

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EE434 ASIC & Digital Systems

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  1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

  2. Digital Design with VHDL Lecture 15

  3. Resolved Signals • A resolution function is used to compute a value for a signal based on multiple drivers • The resolution function computes the value which is used to update the current signal value, depending on the actual values of the drivers.

  4. Resolution Function architecture Example of ... is type Bit4 is (‘X’,’0’,’1’,’Z’); type B_Vector is array (Integer range <>) of Bit4; function Wired_Or(Input: B_Vector) return Bit4 is variable Result: Bit4:=’0’; begin for I in Input’range loop if Input(I)=’1’ then Result:=’1’; exit; elsif Input(I)=’X’ then Result:=’X’; end if; end loop; return Result; end Wired_or; signal Line: Wired_Or Bit4; … P1: process … Line <= ’1’; … P2: process … Line <= ’2’; … end Example

  5. Overloading Operators • An overloaded operator is one for which there is a user-defined function that handles an operation for various data types. • The ‘+’ operator is defined to operate on numeric types. • To add a constant integer to a signal of type std_logic an overloaded operator is needed. • The overloaded operator uses a function that defines the operator for the given types.

  6. Overloaded Operators use work.myops.all; architecture archcounter of counter is begin Upcount: process (clk, rst, pst) begin if rst = ‘1’ then count <= “0000”; elsif pst = ‘1’ then count <= “1111”; elsif (clk ‘event and clk =‘1’) then if load = ‘1’ then count<= data; elsif counten=‘1’ then count <= count+1; end if; end if; end process; end archcounter;

  7. Overloaded Operators (Cont’d) package myops is function “+” (a, b : bit_vector) return bit_vector; function “+” (a : bit_vector; b: integer) return bit_vector; end myops; use work.my_package.all; package body myops is function “+” (a, b : bit_vector) return bit_vector is ………… function “+” (a : bit_vector; b: integer) return bit_vector is ……… begin return (a + i2bv(b, a’length) ); end “+”; end myops;

  8. Arithmetic Operators library ieee; use ieee.std_logic_1164.all; use work.std_arith.all; entity add_vec is port ( a, b, c : in std_logic_vector (3 downto 0); sum1, sum2 : out std_logic_vector (3 downto 0)); end add_vec; architecture adder of add_vec is begin sum1 <=a + b; sum2 <=c + 2; end;

  9. Overloading Functions Functions can be overloaded package majorities is function majority (a, b, c : std_logic) return std_logic; function majority (a, b, c, d : std_logic) returnstd_logic; function majority (vec: std_logic_vector) returnstd_logic; end majorities; package body majorities is function majority (a, b, c : std_logic) return std_logic is begin return ((a and b) or (a and c) or (b and c)); end majority; function majority (a, b, c, d : std_logic) returnstd_logic is begin return ((a and b and c) or (a and b and d) or (a and c and d) or (b and c and d)); end majority; … end package body;

  10. Shift Operations • Shift_left function • Shift a vector to left, replacing the bits on the right-hand side with zeros • Rotate Left • The bits shifted out are used to replace those left empty on the opposite side x <= a sll 2; => x<=a (5 downto 0) & “00”; y <= a rol 2; => y<=a (5 downto 0) & a(7 downto 6);

  11. Assertion Statement • Assertions supplement the modeling of input/output behavior by describing design intent or constraints. • Constraints include illegal inputs (e.g. S = R= 1 for an RS flip-flop), unsupported operating modes, and required synchronized signal transitions. • If the asserted condition fails during simulation (i.e. the condition evaluates to false), an assertion violation occurs. • The violation can be recorded using a reportclause and a severityclause according to the format shown to the right. architecture trial of SR_FF is begin set_reset : process(S, R) is begin assert not (S=‘1’ and R=‘1’) report “illegal input S=R=1” severity ERROR; if S=‘1’ then Q <= ‘1’; end if; if R=‘1’ then Q <= ‘0’; end if; end process set_reset; end trial;

  12. Assertion (Cont’d) function i2bv (val, width : integer) return bit_vector is variable result : bit_vector (0 to width-1):=(others =>’0’); variable bits : integer :=width; begin if (bits > 32) then bits := 32; else assert 2**bits >val report “value too big for bit_vector width” severity warning; end if; end function;

  13. Test Bench • Functional verification • Executable VHDL model, which instantiates the device under test (DUT) • Drives the DUT with a set of test vectors • Compares the response with the expected response (golden) • Test bench is at the top level of the design hierarchy • Provides the capability of testing the DUT through simulation (RTL/gate-level/post-layout)

  14. Simple Test Bench Test the operation of a NAND gate libraryieee; use ieee.std_logic_1164.all; usework.nandgate; -- The top level entity of the test bench has no ports entitytestnandis end testnand ; architecture stimulus oftestnandis --- declare the lower level entity component NAND port (a, b : instd_logic; y : outstd_logic); end component;

  15. Simple Test Bench (Cont’d) --declare local signals to assign values to a, b and observe y signal a, b, y : std_logic; begin ---- create an instance of the NAND gate DUT: port map (a=>a, b=>b, y=>y); -- define a process to apply stimulus process constant PERIOD: time := 40 ns; begin A <= '1';   B <= '1'; wait for PERIOD; assert (Y = '0') report "Test failed!" severity ERROR; -- similarly feed other test vectors ...

  16. Test Bench for a Shifter DUT: shifter port map (Clk, Rst, Load, Data, Q); CLOCK: process begin Clk <= '1'; wait for PERIOD/2; Clk <= '0'; wait for PERIOD/2; end process; INPUTS: process begin wait for PERIOD/2; Rst <= '1'; Data <= "00000000"; Load <= '0'; wait for PERIOD; Rst <= '0'; wait for PERIOD; Data <= "00001111"; Load <= '1'; wait for PERIOD; Load <= '0'; wait for PERIOD*4; ……………..

  17. Testing a simple Processor Refer to the architecture of the processor of lecture 13 libraryieee; use ieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; usework.constant_lib.all; entity TB_MP is end TB_MP; architecturebehvof TB_MP is component microprocessor is port (cpu_clk: instd_logic; cpu_rst: instd_logic; cpu_output: out std_logic_vector(15 downto 0) ); end component; entity processor is port (clk: instd_logic; reset: instd_logic; output: outstd_logic_vector (15 downto 0)); end processor;

  18. Testing a simple Processor (Cont’d) signal TB_clk: std_logic; signal TB_rst: std_logic; signal TB_output: std_logic_vector(15 downto 0); begin Unit: microprocessor port map(TB_clk, TB_rst, TB_output); process begin TB_clk <= '0'; -- offer clock signal in concurrent process wait for 5 ns; TB_clk <= '1'; wait for 5 ns; end process; process begin TB_rst <= '1'; wait for 50 ns; TB_rst <= '0'; wait for 100000 ns; end process; end behv;

  19. Record Types An object of a record type has multiple elements of different types typeiocellis record buffer_inp : bit_vector (7 downto 0); enable : bit; buffer_out : bit_vector (7 downto 0); end record; signalbusa, busb, busc : iocell; signalvec : bit_vector (7 downto 0); busa.buffer_inp <= vec; busb.buffer_inp <= busa.buffer_inp;

  20. Tabular Approach type test_vector isrecord clk, rst : std_logic; cnt : std_logic_vector (2 downto 0); end record; type test_vector_array is array (natural range <>) of test_vector; constant test_vectors : test_vector_array := ( -----reset the counter (clk => ‘0’, rst => ‘1’, cnt => “000”), (clk => ‘1’, rst => ‘1’, cnt => “000”), (clk => ‘0’, rst => ‘0’, cnt => “000”), -----clock the counter (clk => ‘1’, rst => ‘0’, cnt => “001”), (clk => ‘0’, rst => ‘0’, cnt => “001”), (clk => ‘1’, rst => ‘0’, cnt => “010”), (clk => ‘0’, rst => ‘0’, cnt => “010”), …………………….

  21. Tabular Approach (Cont’d) --apply test vectors and test the results verify : process variable vector : test_vector; variable errors : boolean := false; begin for i in test_vectors’range loop ------get vector i vector := test_vectors (i); -----schedule vector i clk <= vector.clk; rst <= vector.rst;

  22. Tabular Approach (Cont’d) ---wait for the circuit to settle wait for 1 ns; --check output vectors if cnt /= vector.cnt then assert false report “cnt is wrong value” errors := true; end if; end loop;

  23. File I/O Approach Applying large number of test vectors procedure Readline (F: in Text; L: out Line); -------reads in a line from a file procedure Writeline (F: out Text; L: in Line); -------writes a line to a file procedure Read (L : inout Line; Value: outstd_logic; Good: outboolean); -- Attempts to read a std_logic value from the beginning of the line. If the value read is a std_logic value, then good returns the value true; otherwise it returns false procedure Read (L :inout Line; Value: outstd_logic); --reads a standard logic value from a line procedure Write (L : inout Line; Value : instd_logic; justified : in Side:= Right; Field: in Width := 0);

  24. Creating test vector file Reads file “memory.inp” and writes file “memory.out”.

  25. Test Process using File I/O use std.textio.all; use work.myio.all; -- rest of the declarations till component instantiation are the same as before -- Test process starts here test : process file vector_file : text is in “memory.inp”; file output_file : text is out “memory.out”; variable invecs, outvecs : line; variable good : boolean; variable ch : character; variable vbus_id : std_logic_vector (7 downto 0); variable vreset, vread_write, vready, vburst : std_logic; variable out_vec : std_logic_vector (3 downto 0)

  26. Test Process using File I/O (Cont’d) begin while not endfile (vector_file) loop ----read a line from the file Readline (vector_file, invecs); ----skip line if it does not begin with a tab Read (invecs, ch, good); if not good or ch /= HT then next; end if; ---- skip line if next value is not a std_logic Read (invecs, vreset, good); next when not good;

  27. Test Process using File I/O (Cont’d) ---found a vector --read vreset, vread_write, vready, vburst, vbus_id with tabs in between Read (invecs, ch); Read (invecs, vread_write); Read (invecs, ch); Read (invecs, vready); Read (invecs, ch); Read (invecs, vburst); Read (invecs, ch); Read (invecs, vbus_id); //wait before scheduling the vector// wait for 10 ns;

  28. Test Process using File I/O (Cont’d) ----schedule vectors reset <= vreset; read_write <=vread_write; ready <= vready; burst <= vburst; bus_id <= vbus_id; wait for 10 ns; out_vec := oe & we & addr; Write (outvecs, out_vec); Writeline (output_file, outvecs); Clk <= not (clk); Wait for 20 ns; Clk <= not (clk) after 10 ns; end loop; -- while not endfile (vector_file)

  29. Summary

  30. Lab Details • Source files (VHDL): http://www.eecs.wsu.edu/~ee434/Labs/ee434.zip • In your UNIX home area • mkdir ee434 • mkdir ee434/lab0 • Copy the two VHDL files to ee434/lab0 • Setup and run Synopsys according to guidelines provided in http://www.eecs.wsu.edu/~ee434/Labs/Synopsys%20basic%20steps.pdf

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