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Chapter 5 Register Transfer Languages

Chapter 5 Register Transfer Languages. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL. Chapter Outline. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation. Micro-operations. Example: X  Y. X.

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Chapter 5 Register Transfer Languages

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  1. Chapter 5Register Transfer Languages

  2. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL Chapter Outline

  3. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation Micro-operations

  4. Example: X  Y X

  5. Specify micro-operations and when they occur Format: conditions: micro-operations Register Transfer Language

  6. Example: α: X  Y X

  7. α: X  Y, Y  Z Simultaneous Data Transfers Q D

  8. α: X  Y, X  Z Invalid Simultaneous Transfers

  9. α: X  0 β: X  1 Loading Constant Values into Registers

  10. Making Transfers Mutually Exclusive

  11. α: X  Y Multi-bit Data Transfers

  12. Bit and Bit-range Transfers

  13. Arithmetic and Logical Micro-operations

  14. Shift Micro-operations

  15. Specifying Digital Components: D Flip-Flop

  16. Specifying Digital Components: JK Flip-Flop

  17. Specifying Digital Components: Left Shift Register

  18. Specifying Simple Systems

  19. System Implementation – Data Paths

  20. System Implementation – Data Paths and Control

  21. System Implementation Using a Bus and 3-State Buffers

  22. System Implementation Using a Bus and a Multiplexer n o j

  23. Counts up when U = 1 Count sequence: 000 001  010  011  100  101  000 … V is 3-bit output = count value C is 1-bit output = 1 when V = 000 Modulo 6 Counter

  24. Modulo 6 Counter State Table 1 1 1 1 1 1

  25. Modulo 6 Counter State Diagram

  26. Modulo 6 Counter RTL Specification

  27. Modulo 6 Counter System Implementation

  28. Modulo 6 Counter Another System Implementation

  29. C = 1 when car is at toll booth I[1..0] indicates coin input Outputs R, G, A: Car in toll booth, toll not fully paid: R = 1 Toll paid: G = 1 Car left without paying full toll: R = 1, A = 1 Toll Booth Controller

  30. Toll Booth Controller States

  31. Toll Booth Controller State Table

  32. Toll Booth Controller State Diagram

  33. Toll Booth Controller State Assignments

  34. Converting State Transitions to RTL Code

  35. Converting State Transitions to RTL Code

  36. Toll Booth Controller RTL Specification (excluding outputs)

  37. Toll Booth Controller RTL Specification (outputs)

  38. Formal syntax – portable Platform independent Design for PLDs, ASICs, or custom chips Simulate designs Different levels of abstraction VHDL – VHSIC Hardware Description Language

  39. Library section Entity section Architecture section VHDL Design Structure

  40. library IEEE; use IEEE.std_logic_1164.all; VHDL Library Section

  41. VHDL Entity Section

  42. VHDL Architecture Section

  43. Modulo 6 counter Designed as a state machine VHDL – High Level of Abstraction

  44. Modulo 6 Counter – Library and Entity Sections

  45. Modulo 6 Counter – One State

  46. Architecture Section – State Generation

  47. Architecture Section – State Generation (continued)

  48. Architecture Section – State Transition

  49. VHDL – Low Level of Abstraction

  50. Components Timing Simulation VHDL – Advanced Capabilities

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