ITRS Public Conference Emerging Research Devices

1. ITRS Public ConferenceEmerging Research Devices 2011 ERD Chapter Preparation Jim Hutchby – SRC December 3, 2010

2. Emerging Research Devices Working Group • Hiroyugi Akinaga AIST • Tetsuya Asai Hokkaido U. • Yuji Awano Keio U. • George Bourianoff Intel • Michel Brillouet CEA/LETI • Joe Brewer U. Florida • John Carruthers PSU • Ralph Cavin SRC • An Chen GLFOUNDRIES • U-In Chung Samsung • Byung Jin Cho KAIST • Sung Woong Chung Hynix • Luigi Colombo TI • Shamik Das Mitre • Erik DeBenedictis SNL • Simon Deleonibus LETI • Bob Fontana IBM • Paul Franzon NCSU • Akira Fujiwara NTT • Christian Gamrat CEA • Mike Garner Intel • Dan Hammerstrom PSU • Wilfried Haensch IBM • Tsuyoshi Hasegawa NIMS • Shigenori Hayashi Matsushita • Dan Herr SRC • Toshiro Hiramoto U. Tokyo • Matsuo Hidaka ISTEK • Jim Hutchby SRC • Adrian Ionescu EPFL • Kiyoshi Kawabata Renesas Tech • Seiichiro Kawamura Selete • Rick Kiehl U. C. Davis • Suhwan Kim Seoul Nation U • Hyoungjoon Kim Samsung • Atsuhiro Kinoshita Toshiba • Dae-Hong Ko Yonsei U. • Hiroshi Kotaki Sharp • Mark Kryder INSIC • Zoran Krivokapic GLOBALFOUNDRIES • Kee-Won Kwon Seong Kyun Kwan U. • Jong-Ho Lee Hanyang U. • Lou Lome IDA • Hiroshi Mizuta U. Southampton • Kwok Ng SRC • Fumiyuki Nihei NEC • Ferdinand Peper NICT • Yaw Obeng NIST • Dave Roberts Nantero • Barry Schechtman INSIC • Kaushal Singh AMAT • Sadas Shankar Intel • Atsushi Shiota JSR Micro • Satoshi Sugahara Tokyo Tech • Shin-ichi Takagi U. Tokyo • Ken Uchida Toshiba • Thomas Vogelsang Rambus • Yasuo Wada Toyo U. • Rainer Waser RWTH A • Franz Widdershoven NXP • Jeff Welser NRI/IBM • Philip Wong Stanford U. • Dirk Wouters IMEC • Kojiro Yagami Sony • David Yeh SRC/TI • Hiroaki Yoda Toshiba • In-K Yoo SAIT • Yuegang Zhang LLLab • Victor Zhirnov SRC

3. Evolution of Extended CMOS Elements Existing technologies More Than Moore ERD-WG in Japan New technologies Beyond CMOS year

4. 2010-2011 ERD/ERM Workshops Co-sponsored by the National Science Foundation

5. Changed Scope of Emerging Research Devices Chapter • Scope of Emerging Research Memory Devices changed in 2011 to include: • New “Storage Class Memory” Subsection • New Memory Select Device Subsection • Scope of Emerging Research Logic • Transition of InGaAs & Ge alternate channel MOSFETs to PIDS & FEP. • Synchronize better with the Nanoelectronics Research Initiative (NRI) • New More-than-Moore Section • Expanded Architecture Secton

6. 2011 ERD Chapter • Emerging Memory Devices • Emerging Logic Devices • Emerging Architectures

7. 2009 Memory Technology Entries Resistive Memories • Redox Memory • Nanoionic memory • Electrochemical memory • Fuse/Antifuse memory • Molecular Memory • Spin Transfer Torque MRAM • Nanoelectromechanical • Nanowire PCM • Macromolecular (Polymer) Capacitive Memory • Electronic Effects Memory • Charge trapping • Metal-Insulator Transition • FE barrier effects • FeFET Memory

8. 2011 Memory Technology Entries Resistive Memories • Redox Memory • Nanoionic memory • Electrochemical memory • Fuse/Antifuse memory • Molecular Memory • Spin Transfer Torque MRAM • Nanoelectromechanical • Nanowire PCM • Macromolecular (Polymer) Capacitive Memory • Electronic Effects Memory • Charge trapping • Metal-Insulator Transition • FE barrier effects • FeFET Memory

9. Workshop (For each of eight technologies) (April 6) Receive expert inputs (pro & con) Clarify status, potential, and remaining challenges Formulate discussion/decision points to be considered in the Wednesday ERD/ERM meeting ERD/ERM Working Group Meeting (April 7) Discuss and reach approximate consensus on potential & challenges for each technology Determine whether any of the eight candidate memory technologies is sufficiently promising and mature to benefit from accelerated development (Scale beyond the 16nm generation) ERD/ERM Memory Technology Assessment Workshop

10. ERD/ERM Memory Technology Assessment Workshop ITRS ERD/ERM identified two emerging memory technologies for accelerated research & development: 1)STT-MRAM and 2) Redox Resistive RAM Redox Memory Cell STT-Memory Cell

11. One Diode – One Resistor (1D1R) Memory Cell Select Device = Diode H-S. P. Wong – Stanford U.

12. Include Storage Class Memory Include Select Device Transfer Nanowire Phase-Change Memory to Transition Table and to PIDS and FEP Transfer Spin Transfer Torque Magnetic RAM (STT-MRAM) to Transition Table and to PIDS and FEP Reorganize emerging research memory classifications – New category named “Redox” RRAM . Content changes for Emerging Research Memory Section

13. 2009 ERD Chapter • Emerging Memory Devices • Emerging Logic Devices • Emerging Architectures

14. 2009 Logic Technology Tables Table 1 – MOSFETs Extending MOSFETs to the End of the Roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non-conventional Geometry Devices Table 3 - Non-FET, Non Charge-based ‘Beyond CMOS’ devices _______________ Collective Magnetic Devices Moving domain wall devices Atomic Switch Molecular Switch Pseudo-spintronic Devices Nanomagnetic (M:QCA) Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET

15. 2011 Logic Technology Tables Table 1 – MOSFETs Extending MOSFETs to the End of the Roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non-conventional Geometry Devices Table 3 - Non-FET, Non Charge-based ‘Beyond CMOS’ Devices _______________ Collective Magnetic Devices Spin Transfer Torque Logic Moving domain wall devices Pseudo-spintronic Devices Nanomagnetic (M:QCA) Molecular Switch Atomic Switch Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET Excitonic FET Mott FET

16. ERD/ERM Logic Technology Recommended Focus: Carbon-based Nanoelectronics – Carbon Nanotubes and Graphene Graphene quantum dot Band gap engineered Graphene nanoribbons FET (Manchester group) Nonconventional Devices Graphene Veselago lense Graphene pseudospintronics Graphene Spintronics Son et al.Nature (07) Cheianov et al.Science (07) Trauzettel et al.Nature Phys. (07) Conventional Devices P. Kim – Columbia U.

17. Add a new section on More-than-More with a focus on devices for wireless applications Transfer InGaAs and Ge MOSFETs to PIDS & FEP Complete transfer of unconventional geometry MOSFETs to PIDS & FEP Transfer SET to More-than-Moore section Add spin transfer torque (STT) majority gate logic Add Mott FET device . Content changes for Emerging Research Logic Section

18. 2009 ERD Chapter • Emerging Memory Devices • Emerging Logic Devices • Emerging Architectures

19. Four Architectural Projections • Hardware Accelerators execute selected functions faster than software performing it on the CPU. • Alternative switches often exhibit emergent, idiosyncratic behavior. They also maybe non-volatile. We should exploit them. • CMOS is not going away anytime soon. • New switches may improve high utilization accelerators

20. Matching Logic Functions & New Switch Behaviors New Switch Ideas Popular Accelerators Single Spin Spin Domain Tunnel-FETs NEMS MQCA Molecular Bio-inspired CMOL Excitonics Encrypt / Decrypt Compr / Decompr Reg. Expression Scan Discrete COS Trnsfrm Bit Serial Operations H.264 Std Filtering DSP, A/D, D/A Viterbi Algorithms Image, Graphics ? Example: Cryptography Hardware Acceleration Operations required: Rotate, Byte Alignment, EXORs, Multiply, Table Lookup Circuits used in Accel: Transmission Gates (“T-Gates”) New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay. Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.

21. Emerging Architectures • Benchmarking Devices • Memory • Architecture for Inference (e.g. Morphic )

22. Emerging Architectures • Benchmarking Devices (moved to Critical Review) • Memory • Architectures (Expanded )

23. Preparing for re-write of 2011 ERD Chapter With ERM, conducting five FxF workshops co-sponsored by NSF Memory Technology Assessment Workshop (April 2010) Graphene-based and spin-based logic devices (Sept. 2010) Materials issues with Redox-RRAM & STT-MRAM (Nov 2010) III- V MOSFETs: Performance assessment and gating issues (Dec.2010) More than Moore Workshop (April 2011) Logic Devices Transferring InGaAs n-channel and Ge p-channel MOSFET technologies from ERD and ERM to PIDS and FEP in 2011 Transfer non-conventional geometry MOSFETs to PIDS/FEP in 2011 Memory Devices A new taxonomy for categorizing resistive memories introduced. An assessment of new memory devices was completed: STT-MRAM and Redox-RRAM identified for accelerated research and development STT-MRAM & NW PCM proposed to fully transfer to PIDS and FEP in 2011 Will expand scope of memory section to include Storage Class Memory & Select Device Adding a new section for More-than-Moore Emerging Research Technologies Architecture Expanding Architectural Section to include several new approaches Update Memory Architecture section ERD – Key Messages