1 / 9

ADC12J4000, TSW14J10, VC707 Dec 4x

ADC12J4000, TSW14J10, VC707 Dec 4x. Test Setup: Single tone is given as input to the device. Test conditions: Fs = internal 4GHz Fin = 60 0MHz Dec 4 P54 mode LMK = 2GHz, clock dist mode VC707 Ref clock = 500MHz (/4 for LMK) VC707 Core clock = 250MHz (/8 for LMK) Lane Rate = 10G

devin-huff
Download Presentation

ADC12J4000, TSW14J10, VC707 Dec 4x

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ADC12J4000, TSW14J10, VC707 Dec 4x

  2. Test Setup: • Single tone is given as input to the device. • Test conditions: • Fs = internal 4GHz • Fin = 600MHz • Dec 4 P54 mode • LMK = 2GHz, clock dist mode • VC707 Ref clock = 500MHz (/4 for LMK) • VC707 Core clock = 250MHz (/8 for LMK) • Lane Rate = 10G • V2p8 firmware

  3. On ADC GUI, load the values as shown below

  4. On ADC GUI, load the values as shown below

  5. On ADC GUI, load the Preset 0 Frequency value as shown below

  6. In Low Level View tab, set LMK04828 address 0x110 to 0x04 to set VC707 REFCLK = 500MHz

  7. In Low Level View tab, set LMK04828 address 0x100 to 0x08 for VC707 Core CLK = 250MHz

  8. Open HSDCD Pro, select “ADC12J4000_D4_DDR”, Enter “1G” for ADC Output Data Rate

  9. Capture results using a 600MHz input tone

More Related