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Adc12j4000 - PowerPoint PPT Presentation

ADC12J4000, TSW14J10, VC707 Dec 4x

ADC12J4000, TSW14J10, VC707 Dec 4x. Test Setup: Single tone is given as input to the device. Test conditions: Fs = internal 4GHz Fin = 60 0MHz Dec 4 P54 mode LMK = 2GHz, clock dist mode VC707 Ref clock = 500MHz (/4 for LMK) VC707 Core clock = 250MHz (/8 for LMK) Lane Rate = 10G

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95 views • 9 slides

ADC12J4000, TSW14J10, VC707 Dec 10x

ADC12J4000, TSW14J10, VC707 Dec 10x. Test Setup: Single tone is given as input to the device. Test conditions: Fs = internal 4GHz Fin = 600MHz Dec 10 LMF = 222, Lane Rate = Fs * 10 *F/S = 400M * 10 * 2 = 8G LMK = 2GHz, clock dist mode

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98 views • 9 slides

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Adc12j4000 - PowerPoint PPT Presentation

ADC12J4000, TSW14J10, VC707 Dec 4x

ADC12J4000, TSW14J10, VC707 Dec 10x