ECE 342 Solid-State Devices & Circuits 17. Differential Amplifiers

1. ECE 342 Solid-State Devices & Circuits 17. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu

2. Background • Differential Amplifiers • The input stage of every op amp is a differential amplifier • Immunity to temperature effects • Ability to amplify dc signals • Well-suited for IC fabrication because • (a) they depend on matching of elements • (b) they use more components • Less sensitive to noise and interference • Enable to bias amplifier and connect to other stage without the use of coupling capacitors

3. Differential Amplifiers • Practical Considerations • Both inputs to a differential amplifier may have different voltages applied to them • In the ideal situation with perfectly symmetric stages, the common-mode input would lead to zero output • Temperature drifts in each stage are often common-mode signals • Power supply noise is a common-mode signal and has little effect on the output signal

4. MOS Differential Pair • Assume current source is ideal • Transistors should not enter triode region

5. Common-Mode Operation • Input voltage vcm to both gates • Difference in voltage between the two drains is zero

6. Differential Input Voltage • Differential pair responds to differntial input signals by providing corresponding differential output signal between the two drains.

7. MOS Differential Pair • Assume current source is ideal • vID=vgs1-vgs2 • Output is collected as vD2-vD1

8. MOS Differential Pair • If vID is positive, vD2-vD1 is positive • vID>0  vgs1>vgs2 ID1 > ID2 • vD1 lower voltage point than vD2 For proper operation, MOSFETS should not enter triode region

9. DC Analysis

10. Incremental Analysis • Neglecting the body effect

11. Frequency Response When driven by a low-impedance signal source, the upper corner frequency is determined by the output circuit

12. Common-Mode Rejection Ratio Assume RSS >> 1/gm

13. Common-Mode Rejection Ratio (a) For single-ended output:

14. Common-Mode Rejection Ratio (b) For differential output:

15. BJT Differential Pair Assume perfect match between the devices and symmetry in the circuit

16. BJT Differential Pair Base currents:

17. BJT Differential Pair – Incremental Model Single-ended gain of first stage: Double-ended differential gain (with vout=vo2-vo1):

18. BJT Differential Pair – General

19. Differential Amplifiers - Observations • Observations • The differential pair attenuates the input signal of each stage by a factor of one-half cutting the gain of each stage by one-half • The double-ended output causes the two single-ended gains to be additive • Thus, the voltage gain of a perfectly matched differential stage is equal to that of a single stage

20. Remarks on Differential Amplifiers • In many applications, the differential amplifier is not fed in a complementary fashion • Rather, the input signal may be applied to one of the input terminals while the other terminal is grounded • In this case, the signal voltage at the emitters will not be zero and thus the resistor REE will have an effect on the operation • However, if REE is large (REE >> re) as is usually the case, vid will still divide equally between the 2 junctions • The operation of the differential amplifier will still be almost identical to that of the symmetrical feed and the CE equivalence can still be employed

21. Common Mode Can show that

22. BJT Diff Pair - Common Mode

23. Example - I b=100 Collector resistance accurate within 1% Early voltage = 100V

24. Example – I (cont’) Emitter current in both transistors is: 0.5 mA

25. Example - I (cont’) Overall differential gain: Where DRC is the worst case variation in collector resistance

26. Example – I (cont’) Common-Mode Rejection ratio CMRR

27. Example – I (cont’) Input common-mode resistance: Ricm

28. Example - II • In the circuit shown, the dc bias current is 4 mA. If a = 0.993, RB1 = RB2 = RB3 = 1,000 W, RE = 30 W, RC = 1.6 kW, VCC= 10 V, and VBE(on) = 0.7 V, • Calculate the dc collector currents • Calculate the dc or quiescent collector voltages • Calculate the maximum peak value of vout before serious distortion results • Calculate the incremental differential voltage gain of the circuit • If the base resistor of Q2 is changed to RB2= 400 W, calculate the dc collector current through each device

29. Example - II

30. Example - II (a) Assuming perfect match between Q1 and Q2, DC bias current will split equally IE1 = IE2 = 2mA. IC=aIE=1.986 mA (b) The quiescent collector voltages will equal (c) Maximum collector voltage is 10 V (at cutoff) minimum is 0 V (at saturation).Therefore, positive peak voltage is 10-6.82 = 3.18 V, and negative peak is 6.82 V p-p voltage = 6.36 V

31. Example - II (d) The incremental differential voltage gain of the circuit is defined as: Calculate re and b

32. Example - II Applying the gain equation and assuming rout >> 1.6 kW gives (e) The voltage at the node above the dc current source can be found from

33. Example - II Effects of non-balance

34. Example - II The corresponding emitter and collector currents are The two quiescent collector voltages are no longer equal, resulting in a nonzero quiescent output voltage

35. Example - II Nonzero quiescent voltage serious consequences when this stage is followed by additional gain stages, creating an output offset voltage when the inputs are shorted together

36. Nonideal Characteristics Input offset voltage of MOS differential pair Mismatch can result in a dc output voltage Vo (output dc offset voltage) Vos=Vo/Ad is input offset voltage

37. Nonideal Characteristics If Vos is applied (differentially) at the input, a zero voltage difference should result at the output • Factors contributing to dc offset voltage • Mismatch in load resistance • Mismatch in W/L • Mismatch in VT

38. Input Offset Voltage for BJT Diff Pair • Offset results from • Mismatch in RC’s • Mismatch in b • Mismatch in junction area

39. Offset Current for BJT Diff Amp In a perfectly symmetric differential pair, the 2 input terminals carry equal dc current to support bias Mismatches (primarily from b) make the 2 input dc currents unequal

40. Differential-to-Single-Ended Conversion • Beyond first stage, signal can be converted from differential to single-ended • Simply ignore the drain current in Q1 and eliminate its drain resistor

41. Differential-to-Single-Ended Conversion • Limitations • Factor of 2 (6 dB) is lost in the gain if drain current of Q1 is not used • Much better approach consists of using drain current of Q1 • Active load approach allows to perform conversion without loss of gain by making use of drain current in Q1

42. MOS Differential Amp with Active Load Replacing drain resistances with current sources, results in much higher voltage gain and savings in chip area in diff amp

43. MOS Differential Amp - Equilibrium

44. MOS Differential Amp with Active Load Current mirror action makes it possible to convert the signal to single-ended form without loss of gain. The differential gain is:

45. MOS Differential Amp with Active Load The active-loaded MOS differential amplifier has a low common-mode gain  high CMRR The common-mode gain is: RSS is internal impedance of current source

46. MOS Differential Amp with Active Load Since RSS is large, Acm will be small

47. BJT Differential Amp with Active Load Current mirror & active load Differential stage

48. Active Loaded BJT Pair – Incremental Model Virtual ground develops at common-emitter terminal

49. BJT Differential Amp with Active Load Output resistance is parallel equivalent of the output resistance of the differential pair and the output resistance of the current mirror The differential gain is: The differential input impedance is:

50. BJT Differential Amp with Active Load The active-loaded BJT differential amplifier has a low common-mode gain  high CMRR The common-mode gain is: REE is internal impedance of current source