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Coordinator - Prof. Swapna Banerjee Co-coordinator - Prof. Chitta Ranjan Mandal SMDP-II Project Report Sponsored b

Indian Institute of Technology, Kharagpur Resource Center. Coordinator - Prof. Swapna Banerjee Co-coordinator - Prof. Chitta Ranjan Mandal SMDP-II Project Report Sponsored by Ministry of Communication & Information Technology, New Delhi. Status of Establishment of VLSI Design Lab.

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Coordinator - Prof. Swapna Banerjee Co-coordinator - Prof. Chitta Ranjan Mandal SMDP-II Project Report Sponsored b

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  1. Indian Institute of Technology, Kharagpur Resource Center Coordinator - Prof. SwapnaBanerjee Co-coordinator - Prof. ChittaRanjanMandal SMDP-II Project Report Sponsored by Ministry of Communication & Information Technology, New Delhi

  2. Status of Establishment of VLSI Design Lab • Laboratory space created : 15 X 7.5 (sq m.) • Photograph of VLSI Lab :

  3. Hardware Utilization

  4. Hardware Purchased

  5. EDA Tools Utilization Summary *Synopsys licenses are not there till 14th January 2012. Temp licenese for 1 month received on 6th Feb 2012.

  6. Books and Furniture Status • No. of books purchased under SMDP-I – 65 • No. of books purchased under SMDP-II – 165 (Till Date) • Furniture procured: Steel Almirahs, Computer Tables, Chairs, Sofa-Set.

  7. Website Preparation • Website has been prepared. Address of website: http://www.smdp.iitkgp.ernet.in • The SMDP website has linked with the IIT Kharagpur main website. Address of the website:http://www.iitkgp.ac.in/acad_n_res_fac NB: ASIC, and FPGA design flow using Xilinx, Cadence, Synopsys video has been uploaded in our website.

  8. IEP Conducted by IIT Kharagpur • IEP on VLSI Aspects in Biomedical Engineering (6-12 March 2011) (Coordinator – Prof. SwapnaBanerjee) 16 participant attended from RCs and PIs • IEP on Low-Power, High-Speed Digital Subsystem Design: Spec-to-test (1st March-13th March 2010) (Coordinator - Prof. Ajit Pal) 14 participants attended from PIs • IEP on TECHNOLOGY CAD (12th May-17th May 2008) (Coordinator - Prof. C.K. Maity) • IEP on VLSI-DSP based design (24th Sep-5th Oct 2007) (Coordinator - Prof. SwapnaBanerjee) • IEP on Low Power VLSI Design (11thSep-22nd Sep 2006) (Coordinator- Prof. Ajit Pal & Prof. SwapnaBanerjee) ** All IEP materials are uploaded in our website (www.smdp.iitkgp.ernet.in)

  9. CAD Tool Training Conducted at IIT Kharagpur • N/A in 2011-2012

  10. International Guest Faculty Workshop 10

  11. International Guest Faculty Workshop • Name of Expert : Prof. Ram Achar • University/ Institution Affiliation : Carleton University, Ottawa, Canada, Ontario-K1S5B6 • Topic of the Lecture : Fundamentals and Advances in VLSI Interconnects & Signal Integrity Methodologies • Date and Duration of the Workshop : 1-3 December 2011 • No. of Participants attended the workshop : 25 • Lecture materials/PPT slides presented to be sent to DIT : IIT KGP did not receive any notes/lecture materials yet.

  12. Laboratory Classes Conducted using the facilities of the SMDP-VLSI Lab ≈ 50 M.Tech/M.S/Ph.D students are doing their research works in SMDP-VLSI Lab.

  13. Manpower Generation

  14. Details of Project Staff Employed

  15. INDIA CHIP PROGRAMME

  16. Chip-I (ICP-KGP-I) Technology - UMCs 180m CMOS Total area - 1.525mm x 1.525mm Foundry - IMEC, Belgium Package type - DIL 40 Number of packaged chips - 10 Current Status - Received The fabrication cost has been paid by IISc Bangalore Number of Blocks - 5 IIT Kharagpur - 2 [10-bit THA] & [4-bit Adder] NIT Durgapur - 1 [6th Order Filter] Jadavpur University - 1 [Chopper Amplifier] BESU - 1 [Clock Generator] Number of pins - 40 [4x10] Power supply - 1.8V (Single) Die Photograph : ICP-KGP-I

  17. Complete Layout with Pads and FillersICP-KGP-I Clock Generator - BESU 10-bit THA - IIT Kharagpur Chopper Amplifier - Jadavpur University 6th Order Filter - NIT Durgapur 4-bit Adder - IIT Kharagpur

  18. 10-Bit, 500MSample/S Track and Hold AmplifierDesigned at IIT Kharagpur Designed by Santosh Kumar Patnaik

  19. Test Results Track/Hold Output Input Sinusoidal Signal (Fin = 500KHz) Sampling Frequency (FS) = 2.5MHz Track/Hold Output Input Sinusoidal Signal (Fin = 4MHz) Sampling Frequency (FS) = 15MHz Designed by Santosh Kumar Patnaik

  20. 4-Bit secure efficient asynchronous adder Designed at IIT Kharagpur Design is not working properly after fabrication

  21. Chip-II (ICP-KGP-II) Technology - UMCs 180m CMOS Total area - 1.525mm x 1.525mm Foundry - IMEC, Belgium Package type - DIL 40 Number of packaged chips - 10 Current Status - Received Fabrication and Packaging Cost - 3160.00 Euro Custom Duty - 13070.00 Rupees Clearance Charge - 5178.00 Rupees Payment – Done [≈ 2,28,166 Rupees] Number of Blocks - 4 IIT Kharagpur - 2 [4-bit ADC] & [4-bit Multiplier] NIT Durgapur - 1 [NOC Generator] Jadavpur University - 1 [Sense Amplifier] Number of pins - 40 [4x10] Power supply - 1.8V (Dual- Analog VDD, Digital VDD) Die Photograph : ICP-KGP-II

  22. Complete Layout with Pads NOC Generator - NIT Durgapur 4-bit SR-ADC - IIT Kharagpur Sense Amplifier - Jadavpur University 4-bit Multiplier - IIT Kharagpur

  23. 4-Bit, 500MSample/S Switched Reference ADCDesigned at IIT Kharagpur Designed by Santosh Kumar Patnaik

  24. Test Results Binary Output Input Sinusoidal Signal (Fin = 15MHz) Sampling Frequency (FS) = 80MHz Binary Output Input Sinusoidal Signal (Fin = 5MHz) Sampling Frequency (FS) = 30MHz Designed by Santosh Kumar Patnaik

  25. 4-Bit Area-power efficient asynchronous adder Designed at IIT Kharagpur Designed by Partha De with Prof C Mandal

  26. Test Results

  27. i) Papers Presented in National / International Conference s in which SMDP-II Financial Support have been used Papers/Publications *** All Papers are listed in our smdp-2 website ****

  28. Best M.Tech Thesis Award

  29. Best M.Tech Thesis Award contd….

  30. Best M.Tech Thesis Award contd….

  31. Financial Status ** Till 31st January 2012

  32. VLSI Placements

  33. VLSI Placements

  34. Reasons for Continuation Manpower Development: Every year more than 200 students are graduated in the field of VLSI who have used the resource of SMDP research lab. Many MS and PhD students are using the facilities available in the SMDP lab for their research work. Few designed chips are on way. Few IP cores has already been generated for specific applications e.g. Biomedical Application, Wireless Communication Application, etc. (One chip has won the Cadence Design Contest 2010 in the Masters Category) ( One design has been awarded as Best paper in TechSym 2011) Every year IEP has been conducted to train the trainer. Few EDA tool training has been organized to cope with the latest VLSI technology. Few International Guest Faculty Programme has been conducted to know the latest research trends in outside of India.

  35. Problem Faced Installation of the software and licensing took more than the scheduled time. 8 HCL Client PC gone down. HCl is taking too much time to repair it. More storage per PC is required for better utilization of the software. Lack of proper EDA tool training programme. Lack of EDA tool up-gradation and licensing ( We don’t have PrimeTime-Power Calculation license).

  36. Chips to Systems Proposal Contour 1. Project Name - An embedded high resolution ultrasonography system using fundamental and harmonic imaging 2. Total Outlay – 541 Lakhs (Including all institute) 3. Duration – 5 Years • Manpower Requirement – @ RC: 2 Research Consultant, 2 Senior Project Assistant, 1 Technician for testing, 1 Job Assistant @PI: 2 Guest Faculty per PI

  37. Software Required for C2S Cadence: 5 year subscription for 20 licenses of each module indicated below • Full Custom/Analog/Mixed Signal/RFIC Design Flow tool set • Functional verification tool set • System design and verification tool set • Logic Design tool set • Digital Implementation tool set • Manufacturability Signoff tool set • IC packaging and SiP design tool set • PCB Design tool set Synopsys: 5 year subscription for 10 licenses of each module indicated below • System Level Design tool set • Digital and analog verification tool set • Implementation and signoff tool set • Manufacturing tool set • TCAD process and device simulation tool set Mentor Graphics: 5 year subscription for tool set available under Mentor Higher Education Programme Xilinx: 5 year subscription for 50 licenses of each module indicated below Software Requirements: Xilinx Latest version with system edition Hardware Requirements: Virtex-6 and Spartan-6 boards

  38. Objective of C2S Main output from the project: Development of JPEG-2000 on ASIC. (IIT KGP, BESU) Development of FFT/IFFT unit (IIT KGP) Development of knowledge base system. (IIT KGP) Telemedicine solution along with the system. (IIT KGP, BESU ) CAM Memory Design (JU) DSP/DIP chips (NIT DGP, IIT KGP, BESU, JU) Portable Low-Cost Ultrasound System design (IIT KGP, PSG College Tech.) Design & Development of image and video processing algorithm (IIT KGP, PSG Coll. Tech, NIT DGP, BESU, JU) Over all System Integration (IIT KGP). Application area in which system would find use: Healthcare Manpower at Ph.D & Masters level proposed to be generated as a secondary outcome of the project: Same as SMDP-II Name of the PIs along with whom collaborative development work would be carried out for designing the identified targeted system: (a) IIT Kharagpur, (b) BESU, Howrah, (c) Jadavpur University, (d) NIT Durgapur, (e) PSG College of Tech. Coimbatore

  39. Year wise Outputs of the C2S

  40. THANK YOU FOR YOUR KIND ATTENTION

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