Digital Hardware Systems: Tri-State Gates and Open-Collector Logic

1. Overview • Last lecture • Digital hardware systems • Today • Tri-state gates and Open-collector wire-AND’s • Digital hardware systems (Processor) CSE 370 – Winter 2002 – Comp.org 1 - 1

2. value C1i C2i C3i mux control C1 C2 C3 4 4 4 mux control + multiplexer 4 value comparator equal 4 equal Data-path implementation (cont’d) • Tri-state logic • utilize a third output state: “no connection” or “float” • connect outputs together as long as only one is “enabled” • open-collector gates canonly output 0, not 1 • can be used to implementlogical AND with only wires oc tri-state driver (can disconnectfrom output) open-collector connection (zero whenever one connection is zero, one otherwise – wired AND) CSE 370 – Winter 2002 – Comp.org 1 - 2

3. In OE OutX 0 Z0 1 01 1 1 Tri-state gates • The third value • logic values: “0”, “1” • don't care: “X” (must be 0 or 1 in real circuit!) • third value or state: “Z” — high impedance, infinite R, no connection • Tri-state gates • additional input – output enable (OE) • output values are 0, 1, and Z • when OE is high, the gate functions normally • when OE is low, the gate is disconnected from wire at output • allows more than one gate to be connected to the same output wire • as long as only one has its output enabled at any one time (otherwise, sparks could fly) OE In Out 100 non-inverting tri-statebuffer In OE Out CSE 370 – Winter 2002 – Comp.org 1 - 3

4. F Input0 OE Input1 OE Select Tri-state and multiplexing • When using tri-state logic • (1) make sure never more than one "driver" for a wire at any one time (pulling high and low at the same time can severely damage circuits) • (2) make sure to only use value on wire when its being driven (using a floating value may cause failures) • Using tri-state gates to implement an economical multiplexer when Select is highInput1 is connected to F when Select is lowInput0 is connected to F this is essentially a 2:1 mux CSE 370 – Winter 2002 – Comp.org 1 - 4

5. Open-collector gates and wired-AND • Open collector: another way to connect gate outputs to the same wire • gate only has the ability to pull its output low • it cannot actively drive the wire high (default – pulled high through resistor) • Wired-AND can be implemented with open collector logic • if A and B are "1", output is actively pulled low • if C and D are "1", output is actively pulled low • if one gate output is low and the other high, then low wins • if both gate outputs are "1", the wire value "floats", pulled high by resistor • low to high transition usually slower than it would have been with a gate pulling high • hence, the two NAND functions are ANDed together with ouputs wired together using "wired-AND"to form (AB)'(CD)' open-collector NAND gates CSE 370 – Winter 2002 – Comp.org 1 - 5

6. Computer organization • Computer design – an application of digital logic design procedures • Computer = processing unit + memory system • Processing unit = control + datapath • Control = finite state machine • inputs = machine instruction, datapath conditions • outputs = register transfer control signals, ALU operation codes • instruction interpretation = instruction fetch, decode, execute • Datapath = functional units + registers • functional units = ALU, multipliers, dividers, etc. • registers = program counter, shifters, storage registers • Memory contains data and instructions (stored program computer) CSE 370 – Winter 2002 – Comp.org 1 - 6

7. address Memory System Processor read/write data central processing unit (CPU) control signals Control Data Path data conditions instruction unit– instruction fetch and interpretation FSM execution unit– functional units and registers Structure of a computer • Block diagram view CSE 370 – Winter 2002 – Comp.org 1 - 7

8. OE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D7 D6 D5 D4 D3 D2 D1 D0 CLK Registers • Selectively loaded – EN or LD input • Output enable – OE input • Multiple registers – group 4 or 8 in parallel to form a 32-bit or 64-bit register • We won’t make that distinction for “a register” OE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance) LD asserted during a lo-to-hi clock transition loads new data into FFs CSE 370 – Winter 2002 – Comp.org 1 - 8

9. MUX MUX MUX MUX rd R4 rt rs rd rs R4 rd rs R4 rt rt MUX BUS Register transfer: Some possibilities • Point-to-point (allows concurrency) connection • dedicated wires • muxes on inputs ofeach register • very costly when lots of registers and/or wide registers • Common input from multiplexer • load enablesfor each register • control signalsfor multiplexer • Common bus with output enables • output enables and loadenables for each register • Allow one register to “broadcast” to several others Common = potential contention and no concurrency CSE 370 – Winter 2002 – Comp.org 1 - 9

10. RE RB RA WE WB WA D3 D2 D1 D0 Q3 Q2 Q1 Q0 Register files • Collections of registers in one package • two-dimensional array of FFs (n registers of m bits) • address (1 out of n) used as index to a particular word (an m-bit register) • can have separate read and write addresses so can do both at same time • 4 by 4 register file • 16 D-FFs organized as four words of four bits each • write-enable (load) • read-enable (output enable) • Register “indexes” are sometimes visible (to assembly language programmers CSE 370 – Winter 2002 – Comp.org 1 - 10

11. RD WR A9 A8 A7 A6 A5 A4 A3 A2 A2 A1 A0 IO3 IO2 IO1 IO0 Memories • Larger collections of storage elements • implemented not as FFs but as much more efficient latches • high-density memories use 1 to 5 switches (transitors) per memory bit • Static RAM – Same organization as ROM (e.g.,1024 words each 4 bits wide) • once written, memory holds forever (not true for denser dynamic RAM) • address lines to select word (10 lines for 1024 words) • read enable • same as output enable • often called chip select • permits connection of manychips into larger array • write enable (same as load enable) • bi-directional data lines • output when reading, input when writing CSE 370 – Winter 2002 – Comp.org 1 - 11