1 / 13

Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Capacitance in a CMOS Circuit. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

hinto
Download Presentation

Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsCapacitance in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC5970-001/6970-001 Lecture 3

  2. Capacitances VDD C1 In Out C2 CW GND ELEC5970-001/6970-001 Lecture 3

  3. Miller Capacitance VDD C1 In Out CM C2 CW GND ELEC5970-001/6970-001 Lecture 3

  4. Before Transition VDD C1 +VDD 0 In Out CM C2 CW GND ELEC5970-001/6970-001 Lecture 3

  5. After Transition VDD Energy from supply = 2 CM VDD2 Effective capacitance = 2 CM C1 -VDD 0 In Out CM C2 CW GND ELEC5970-001/6970-001 Lecture 3

  6. Capacitances in MOSFET Cgs Cgd Gate Gate oxide Source Drain Cg Cd Cs Bulk ELEC5970-001/6970-001 Lecture 3

  7. Bulk nMOSFET Polysilicon Gate Drain W Source n+ n+ L p-type body (bulk) SiO2 Thickness = tox ELEC5970-001/6970-001 Lecture 3

  8. Gate Capacitance Cg = Cox WL = C0, intrinsic cap. Cg = Cpermicron W εox Cpermicron = Cox L = ── L tox where εox=3.9ε0 for Silicon dioxide = 3.9×8.85×10-14 F/cm ELEC5970-001/6970-001 Lecture 3

  9. Intrinsic Capacitances Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78. ELEC5970-001/6970-001 Lecture 3

  10. Low-Power Transistors • Device scaling to reduce capacitance and voltage. • Body bias to reduce threshold voltage and leakage. • Multiple threshold CMOS (MTCMOS). • Silicon on insulator (SOI) ELEC5970-001/6970-001 Lecture 3

  11. Device Scaling • Reduced dimensions • Reduce supply voltage • Reduce capacitances • Reduce delay • Increase leakage due to reduced VDD/ Vt ELEC5970-001/6970-001 Lecture 3

  12. Optimum Threshold Voltage Vt = 0.7V Vt = 0.3V Delay Delay or Energy-delay product Energy-delay product 0 1 2 3 4 5 6 • VDD / Vt ELEC5970-001/6970-001 Lecture 3

  13. Bulk CMOS Inverter Polysilicon (input) SiO2 Output GND VDD metal 1 p+ n+ p+ p+ n+ n+ n-well p-substrate (bulk) ELEC5970-001/6970-001 Lecture 3

More Related