1 / 24

Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Glitch-Free ASICs. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

shing
Download Presentation

Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsDynamic Power: Glitch-Free ASICs Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5970-001/6970-001 Lecture 9

  2. Motivation • Application Specific Integrated Circuit (ASIC) chips employ standard cell design style. • Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design. • Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC. ELEC 5970-001/6970-001 Lecture 9

  3. Power Dissipation in CMOS Logic (0.25µ) Ptotal (0→1) = CL VDD2 + tscVDD Ipeak+VDDIleakage CL %75 %20 %5 ELEC 5970-001/6970-001 Lecture 9

  4. Prior Work: Hazard Filtering Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997. • Glitch is suppressed when the inertial delay of gate exceeds the differential input delay. 2 or 1 or 3 2 Filtering Effect of a gate 2 ELEC 5970-001/6970-001 Lecture 9

  5. Prior Work: A Reduced Constraint Set LP Model for Glitch Removal Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003. • Satisfy glitch suppression condition at all gates: Differential path delay at gate input < inertial delay • Use a linear program (LP) to find delays • Path enumeration avoided • Reduced (linear) size of LP allows scalability • Design gates with specified delays • 40-60% dynamic power savings in custom design • Procedure is not suitable for pre-designed cell libraries ELEC 5970-001/6970-001 Lecture 9

  6. Prior Work: ASIC • J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01 • Transistor sizing results in 20 - 25% savings in power • Power optimized by minimizing parasitic capacitances • No glitch reduction attempted • Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01 • Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints • Sum of dynamic and leakage power is minimized • Library contains cells of varying sizes,supply voltages, and threshold voltages • Achieved 79% power saving on an average • No glitch reduction attempted. ELEC 5970-001/6970-001 Lecture 9

  7. A Glitch-Free Design • Balance differential delays at cell inputs: • Use Resistive Feedthrough cell delay elements • Automate the design • Customized delay cell generation • Insertion into the circuit ELEC 5970-001/6970-001 Lecture 9

  8. Delay Elements • Inverter pair: delay controlled by W/L of transistors. • Diffusion capacitor: n-diffusion, SiO2, polysilicon. • Polysilicon resistor: R□L/W • Sheet resistance (0.25μ CMOS process) • R□= 3.6Ω/square, with silicide • R□= 173.6Ω/square, with silicide masked • Transmission gate ELEC 5970-001/6970-001 Lecture 9

  9. Evaluation of Delay Elements ELEC 5970-001/6970-001 Lecture 9

  10. Comparison of Delay Elements • Resistor shows • Maximum delay • Minimum power and area per unit delay • Hence, best delay element • Resistive feed through cell • A fictitious buffer at logic level III. Polysilicon resistor (15.4kΩ) I. Inverter pair II. n diffusion capacitor(2.7fF) IV. Transmission gate ELEC 5970-001/6970-001 Lecture 9

  11. Resistive Feedthrough Cell • A parameterized cell • Physical design is simple – easily automated • No routing layers(M2 to M5) used – not an obstruction to the router R□*(length of poly) R = Width of poly S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004. ELEC 5970-001/6970-001 Lecture 9

  12. R Vin Vout CL TPLH + TPHL TP = 2 RC Delay Model • CL varies during transition (model not perfectly linear) • Spectre simulation data stored as a 3D lookup table • Average of signal rise and fall delays • Linear interpolation used TP CL R ELEC 5970-001/6970-001 Lecture 9

  13. Design Optimization Flow DesignEntry Find delays from LP Find resistor values from lookup table Tech. Mapping Remove Glitches Generate feed through cells and modify netlist Layout ELEC 5970-001/6970-001 Lecture 9

  14. Results S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004. ELEC 5970-001/6970-001 Lecture 9

  15. Glitch Elimination on net86 in4-bit ALU Source: Post layout simulation in SPECTRE ELEC 5970-001/6970-001 Lecture 9

  16. Layouts of c880 Power saving = 43% Area increase= 98% Optimized layout of c880 Originallayout of c880 ELEC 5970-001/6970-001 Lecture 9

  17. Reference • S. Uppalapati, M. L. Bushnell and V. D. Agrawal, “Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells,” Proc. 9th VLSI Design and Test Symp., Aug. 11-13, 2005, pp. 41-48. ELEC 5970-001/6970-001 Lecture 9

  18. Conclusion • Successfully devised a glitch removal method for the standard cell based design style • Does not require redesign of the library cells • Does not increase the critical path delay • Modified design flow maintains the benefits of ASIC • On an average • Dynamic power saving: 41% • Area overhead: 60% • Possible ways to reduce area overhead • Cell replacements from existing library • On-the-fly-cell design • Adjust routing delays for glitch suppression ELEC 5970-001/6970-001 Lecture 9

  19. Custom Design • Model gates with input and output delays. Delay = d + d1 Input 1 Gate d1 Output delay = d d2 Input 2 0 ≤ d1, d2 ≤ ub Delay = d + d2 ELEC 5970-001/6970-001 Lecture 9

  20. Determination of Delays • Determine the realizable upper bound (ub) on gate input differential delay by simulation of gates and delay elements. • Determine input and output delays for all gates for glitch suppression. • Implement gates with required delays. • References: • T. Raja, V. D. Agrawal and M. L. Bushnell, “Design of Variable Input Delay Logic for Low Dynamic Power Circuits,” Proc. PATMOS, Sep 2005. • T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay Logic and Its Application to Low Power Design,” Proc. 18th Int’l. Conference on VLSI Design, Jan 2005, pp. 596-603. • T. Raja, V. D. Agrawal and M. L. Bushnell, “CMOS Design of Circuits for Minimum Dynamic Power and Highest Speed,” Proc. 17th Int’l. Conference on VLSI Design, Jan 2004, pp. 1035-1040. ELEC 5970-001/6970-001 Lecture 9

  21. Implementation of Delays d1 < d2 Gate delay = d+d1 Delay = d2-d1 VDD ELEC 5970-001/6970-001 Lecture 9

  22. Design of c7552 Circuit Un-optimized Gate Count = 3827 Transistor Count ≈ 40,000 Critical Delay = 2.15 ns Area = 710 x 710 μm2 Optimized Gate Count = 3828 Transistor Count ≈ 45,000 Critical Delay = 2.15 ns Area = 760 x 760 μm2(1.14) ELEC 5970-001/6970-001 Lecture 9

  23. Instantaneous Power by Spice Power Saving: Peak 68%, Average 58% ELEC 5970-001/6970-001 Lecture 9

  24. Energy Measured by Spice Power Saving: Average 58% ELEC 5970-001/6970-001 Lecture 9

More Related